Reconfigurable Gate Array Research Articles

Optical multi-context scrubbing operation on a redundant system.

This paper presents a proposal of the world-first optical multi-context scrubbing operation on a redundant system that can maintain the state of a sequential circuit and the operation continuously without any interruption on a radiation-hardened optically reconfigurable gate array even after a permanent failure suddenly happens on the sequential circuit or a flip-flop by radiation. Up to now, a high-speed optical scrubbing operation has been demonstrated on a radiation-hardened optically reconfigurable gate array. In addition, a multi-context scrubbing operation based on the high-speed optical scrubbing operation has already been demonstrated. Although the multi-context scrubbing operation presents the benefit that it can treat both soft-errors and permanent failures caused by radiation simultaneously, the conventional contributions have never presented how to maintain the state of a sequential circuit after a permanent failure occurs on flip-flops. Therefore, in the conventional multi-context scrubbing operation, all the operations must be restarted from the initial condition each time a permanent failure occurs on a programmable gate array. As a result, conventional multi-context scrubbing operations could not be applied for real-time systems. The proposed optical multi-context scrubbing method that can solve the issue has been experimentally evaluated on a radiation-hardened optically reconfigurable gate array.

Accurate and efficient molecular dynamics based on machine learning and non von Neumann architecture

Force field-based classical molecular dynamics (CMD) is efficient but its potential energy surface (PES) prediction error can be very large. Density functional theory (DFT)-based ab-initio molecular dynamics (AIMD) is accurate but computational cost limits its applications to small systems. Here, we propose a molecular dynamics (MD) methodology which can simultaneously achieve both AIMD-level high accuracy and CMD-level high efficiency. The high accuracy is achieved by exploiting deep neural network (DNN)’s arbitrarily-high precision to fit PES. The high efficiency is achieved by deploying multiplication-less DNN on a carefully-optimized special-purpose non von Neumann (NvN) computer to mitigate the performance-limiting data shuttling (i.e., ‘memory wall bottleneck’). By testing on different molecules and bulk systems, we show that the proposed MD methodology is generally-applicable to various MD tasks. The proposed MD methodology has been deployed on an in-house computing server based on reconfigurable field programmable gate array (FPGA), which is freely available at http://nvnmd.picp.vip.

Analysis of optical properties and internal structures of γ-ray-irradiated holographic devices formed using liquid crystal composites

A holographic memory with optical writing information for an optically reconfigurable gate array was fabricated and investigated under increasing γ-ray irradiation doses. The bright spot pattern in a 20 × 17 array, reconstructed from the holographic memory, was correctly reproduced with an increasing radiation dose till 300 Mrad. The diffraction efficiency corresponding to each bright spot was maintained at a high value of 50% and, in some cases, over 60%, indicating radiation resistance up to a total dose of 300 Mrad. In addition, four holographic devices, formed via the same process and under similar conditions using liquid crystal composites, were simultaneously used to evaluate the differences among the multiple samples through polarizing optical microscopy and scanning electron microscopy.

A new radiation-hardened architecture for holographic memory address calculation

Architectures for the memory address calculation unit of a holographic memory device have been deeply analyzed in the literature. Finite-precision analysis and the selection of parameters to ensure a discrepancy between the hologram plane and the observation plane of less than 1% has been performed by other designers. However, a fault-tolerant architecture implemented on field-programmable gate array (FPGA) for an Optically Reconfigurable Gate Array has not been proposed yet. Due to the importance of this unit in environments with high levels of radiation, such as robots in nuclear disasters or satellites in space, which are the most common applications, there is a real interest in protecting this hardware. This work introduces two main contributions: i) replaces the calculation of distances through a Coordinate Rotation Digital Computer (CORDIC) unit in order to save area and ii) improves the ratio of fault-detection and extends the input range of the trigonometric computations to exploit more efficient error detection techniques. The derived architecture allows us to recover the FPGA from a faulty behavior in 95% of the cases, which avoids waiting for slower processes such as scrubbing. This real-time detection only requires an extra area of 13% with respect to the unprotected circuit and does not include any loss of precision compared to previous designs.

Improved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic Systems

To be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic system under loading conditions and atmospheric data (temperature and irradiance). The goal of this controller is to prove that the FLC is the best technique of MPPT to extract the maximum power of photovoltaic modules. The main objective of this work is the implementation on a “Cyclone II” circuit using “EP2C35F672C6” Development Board reconfigurable Field-Programmable Gate Array (FPGA) with Hardware Description Language (VHDL). Thus, we show the advantages of using the FPGA circuits, which are their short progress time, their low price and their suppleness of process. The close optimum design of this technique is based on the best choice membership functions and control rules for two- input, one-output digital Fuzzy Logic Controller (FLC) based on “Mamdani” mechanism. The simulation and implementation results obtained respectively with waveform under Quartus software and on Cyclone II, both show a satisfactory performance and confirm the good tracking efficacy and speedy response to various atmospheric conditions.

Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs

This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces of its reconfigurable modules, the structure of the communications, the inclusion of specialized modules to handle and optimize circuit reconfiguration at runtime, and the organization of the reconfigurable partitions. We evaluate two methods to select the new target partition for modules in faulty partitions and design their hardware as intellectual property modules. We evaluate the performance and scalability of this approach using a trapezoidal shaper, a filter used to detect high-energy particles in radiation experiments, and we carry out the experiments with a variable number of modules and reconfigurable partitions using the two selection algorithms. The proposal is compared with nonfault-tolerant and triple modular redundancy approaches, and it remains functional with up to $12\times $ more injected faults than those.

Optically reconfigurable gate array using a colored configuration.

This paper presents a proposal of an optically reconfigurable gate array using a colored configuration. The optically reconfigurable gate array consists of a very-large-scale integration (VLSI), a holographic memory, and four lasers with different wavelengths. The optically reconfigurable gate array VLSI includes a fine-grained programmable gate array as well as field programmable gate arrays. Four configuration contexts can be stored on the holographic memory and can be programmed onto the programmable gate array VLSI addressed by the four lasers. This paper presents the demonstration of the optically reconfigurable gate array using a colored configuration.

Three-dimensional artificial organism model developed upon a two-layer coarse-fine-grid network approach

In an attempt to devise a model which more closely imitates cellular biology a three-dimensional (3D) artificial organism model developed upon a two-layer coarse-fine-grid network model is proposed in this paper. The strength of this original approach is that it endeavors to capture the complexity of both the cellular networks as well as that of the biological cell itself, by implementing the internal biological phenomena of an organism into a 3D two different network topology hardware layer. In essence, this model not only keeps the full advantages of previously created 2D models that enable the implementation of similar self-replicating or selfrepairing abilities akin to those expressed by its cellular equivalents in nature, but there the inherent need of artificial cell structures to fulfill the entire role of a biological cell in the network is also expressed. Computer-aided simulation results prove that this kind of 3D coarse-fine-grid approach is well feasible physically therefore the model has been implemented into a computing platform made of custom reconfigurable Field Programmable Gate Array (FPGA) processors.

Tolerance of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation.

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are discussed in the application for an optically reconfigurable gate array. The radiation experiments are conducted using a cobalt 60 gamma radiation source to examine the tolerance of a 100Mrad total ionizing dose for the HPDLC memory. The optical properties are compared in the conditions before and after gamma-ray irradiation for the fabricated HPDLC gratings. The effects of gamma-ray irradiation on the internal grating structure are also investigated by polarization optical microscopy and scanning electron microscopy observations. The HPDLC memory irradiated by a 100Mrad total ionizing dose demonstrates the implementation of the optical reconfiguration in a gate-array VLSI.

High-speed scrubbing demonstration using an optically reconfigurable gate array.

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs.

Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 × 3 in.2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer (PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy (SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.

Formation of holographic polymer-dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays.

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array is discussed for angle-multiplexing recording by controlling the laser interference exposure in LC composites. The successive laser illumination system to record the various configuration contexts at the specified region and angle in HPDLC memory is constructed by using the combination of a half-mirror and a photomask placed on the motorized stages under the control of a personal computer. The effect of laser exposure energy on the formation of holographic memory is investigated by measuring diffraction intensity as a function of exposure energy during the grating formation process and observing the internal grating structure by scanning electron microscopy. The optical reconfiguration in the gate-array VLSI is executed for configuration contexts of OR and NOR operations shown as logical operators that are reconstructed by laser irradiation at different incident angles for a specified region in the HPDLC memory.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Peak Power and Crest Factor Reduction in OFDM Transceiver Using Filtering Method for SDR Application

The software defined radio is used as a Transceiver system for next generation wireless communication system. The physical layer architecture is presented in this paper. High peak to power average ratio/crest factor is the main challenge of the orthogonal frequency division multiplexing modulation techniques. Here windowing technique with adaptive filtering is applied for the transmitted signal to reduce the power. The black Mann window is used for this purpose. The mapping/de-mapping of signal in the transmitter and receiver is done with various types of modulation. The proposed system requires only one IFFT block for sampling the signals. The existing method such as clipping and filtering gives fare result but there is a chance of losing the peak values of the signal. This issue can be overcome by proposed method. The comparison of power, crest factor and bit error ratio has been taken in MATLAB. This architecture can be done on reconfigurable field programmable gate array.

Self-reconfigurable control architecture for complex mobile robots

Abstract Advanced mobile robot systems need to accomplish increasingly complex task sets. However, to solve demanding problems, they are typically optimized to a very restricted set of tasks and environments. This work will therefore propose a self-reconfigurable software and hardware architecture to allow the dynamic optimization of a robot system depending on the current situation, i. e. the current task, the robot inner state, and the environment. The proposed framework is based on organic computing principles and unsupervised machine learning techniques. It further uses dynamically reconfigurable Field Programmable Gate Arrays (FPGA) as hardware accelerators. Preliminary results will be presented, which demonstrate the feasibility of the self-reconfiguration approach.

A novel FPGA-based architecture for the estimation of the virtual dimensionality in remotely sensed hyperspectral images

A challenging problem in spectral unmixing is how to determine the number of endmembers in a given scene. One of the most popular ways to determine the number of endmembers is by estimating the virtual dimensionality (VD) of the hyperspectral image using the well-known Harsanyi–Farrand–Chang (HFC) method. Due to the complexity and high dimensionality of hyperspectral scenes, this task is computationally expensive. Reconfigurable field-programmable gate arrays (FPGAs) are promising platforms that allow hardware/software codesign and the potential to provide powerful onboard computing capabilities and flexibility at the same time. In this paper, we present the first FPGA design for the HFC-VD algorithm. The proposed method has been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASA’s Airborne Visible Infra-Red Imaging Spectrometer over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that our hardware version of the HFC-VD algorithm can significantly outperform an equivalent software version, which makes our reconfigurable system appealing for onboard hyperspectral data processing. Most important, our implementation exhibits real-time performance with regard to the time that the hyperspectral instrument takes to collect the image data.

A Low-cost Reconfigurable Field-programmable Gate Array Based Three-phase Shunt Active Power Filter for Current Harmonic Elimination and Power Factor Constraints

Non-linear loads, such as switched mode power supply, adjustable-speed drives, arc furnaces, etc., result in deterioration of power quality in terms of current harmonics and reactive power demand. Shunt active power filters are widely used to compensate the current harmonics, thereby improving power quality. Digital signal processors and microcontroller units used in digital control of shunt active power filters are constrained by a complex algorithm structure, adaptability, accuracy, the absence of feedback loop delays, and larger execution time. Shunt active power filters require a faster computation update rate to maintain the closed-loop bandwidth, accurate sensing of voltage and current, proper estimation of parameters, and a high frequency pulse-width modulation. In this article, a low-cost single all-on-chip field-programmable gate array implements the digital control of a three-phase shunt active power filter. This proposed implementation scheme has much less execution time and boosts the overall performance of the system. All required tasks of a typical shunt active power filter are implemented with a low-cost single all-on chip field-programmable gate array module that provides freedom to reconfigure for any other applications. Additional features, such as anti-windup, over-sampling, and time multiplexing, are also added to improve the overall performance. The proposed system is designed to meet IEEE 519 and IEC EN 61000-3 recommendations in terms of harmonic elimination and unity power factor requirements. The entire algorithm is coded, processed, and simulated using Xilinx 12.1 ISE Suite to estimate the advantages of the proposed system. This code is also defused on the low-cost single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype, and experimental results obtained match with simulated counterparts. The proposed control scheme for the shunt active power filter results in reduces current harmonics under dynamic and steady-state operating conditions.

A Temperature Transmitter with Autonomous Reconfiguring Function

In this paper, according to several common temperature sensors in the industrial field a temperature transmitter based on the reconfigurable field programmable gate array (FPGA) has been designed to ensure that a single device which can meet the requirements of the various applications. The transmitter can quickly and automatically identify the sensor type (ST) and connection type (CT) of external temperature sensor (ETS). It then can automatically search the reconfiguration scheme by reconfiguration identification and reconfiguration planning. The transmitter also reconfigures its inner structure by auto-deployment. Therefore, acquisition and processing the temperature with different ST and CT can be realized. In addition, a physical prototype is developed, and the effectiveness of the temperature transmitter with autonomous reconfiguring function (TTARF) is verified in the resistance temperature detector (RTD) application. The whole reconfiguration process is fully automated without human intervention.

RECONFIGURING EVOLVED CIRCUITS USING CONTROLLER: A REAL TIME APPROACH

FPGA is a device that contains a matrix of reconfigurable gate arrays that can implement different complex functions and also vary structurally. In this study, a novel method of reconfigurable circuit switching action is done with the help of a controller. BPSK Modulation application is chosen to demonstrate the reconfigurable action. When an event occurs the context/core switching is done at both input and output and also preserving the structural and functional relationship. The reconfiguration ability of FPGA with an embedded core performing the switching in real time is the focus of this study. A controller running on Linux platform is used along with the FPGA core. In this study, we propose a real time approach for reconfiguring evolved circuits using controller. It has an adaptive hardware that can continuously change in response to the input data and there by perform reconfiguration. Here the reconfiguration process is achieved by using a real time controller which gives a command to the FPGA core (ALTERA (Cypress processor)) for reconfiguration.