Reconfigurable Gate Array Research Articles

A distributed, hardware reconfigurable and packet switched real-time control and data acquisition system

The architecture of a synchronized event-based control and data acquisition system that aims to improve significantly the performance of actual systems is presented. The design explores recent developments in data transport, signal processing and system synchronization. Data transport between the acquisition, processing and storing devices and at backplane level will be performed by InfiniBand, a low latency packet switched network standard. Data processing algorithms will be performed in a mixture of digital signal processors and reconfigurable field programmable gate arrays. Both devices will be programmed from a descriptive high-level mathematical language. Acquisition synchronization, data stamping and event management will be performed through a specialized low latency synchronous optical network for the time critical signals.

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.

On re-configurable methods and gate array based solutions of fast forward error correction systems for software radio and set-top-box applications

Existing communication systems and the corresponding interfaces differ with respect to bandwidth, carrier frequency and modulation patterns. The investigation of digital receivers for processing of multiple standards and modulation schemes within a single system are one of the research topics today. In this paper fast forward error correction units, required for broadband receivers and software radio solutions have been investigated. The proposed FEC systems are based on a radix-2/radix-4 decoding approach and have been verified within high density FPGAs.

An In-Camera Data Stream Processing System for Defect Detection in Web Inspection Tasks

One of the aims of industrial machine vision is to develop computer and electronic systems to replace human vision in quality control of industrial production. Traditionally these systems consist of a line scan camera, host computer, frame grabber and one or more dedicated processing boards. In this paper we discuss the development of a new integrated design environment, developed for real-time defect detection, that eliminates the need for an external frame grabber and other associated host computer peripheral systems. The processing board contains a reconfigurable field programmable gate array FPGA inside a DALSA CCD camera. The FPGA is directly connected to the video data-stream and outputs data to a low bandwidth output bus. The system is targeted for web inspection but has the potential for broader application areas. We describe and show test results of the in-camera prototype system board and discuss some of the algorithms currently simulated and implemented for web inspection applications.

Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters

Adaptive sample rate filtering has been shown to be an efficient and effective method of removing narrowband interference from broadband communication signals. The expression for the gradient for adaptive sample rate filtering is expressed in terms of the traditional adaptive filter gradient. Adaptive algorithms frequently use divide and square operations. Rather than implementing a generic multiplier in the adaptive section for the adaptive sample rate notch filter, we have developed a technique of optimizing an implementation of the squarer. In the sequential reciprocal circuit presented, we show how a numerator (scaling) can be easily incorporated into its design to achieve a general purpose divider. A Synopsis-synthesized VHDL description of a parallel reciprocal circuit is included for comparison. Both realizations have been demonstrated in an adaptive sample rate notch filter which has been downloaded into a single Xilinx XC4010 reconfigurable Field Programmable Gate Array (FPGA).

Adaptive data interleaving using a microprocessor controlled reconfigurable gate array

A reconfigurable gate array allows different circuits to be implemented on a single device. When combined with a microprocessor, used as part of a high density data storage channel, it is possible to implement the time-critical sections of the storage algorithm in dedicated circuits. The storage algorithm can be changed as required by recording channel characteristics, by reconfiguring the gate array to implement different dedicated circuits. Interleaving circuits that increase the burst error correcting capability of recording codes have been implemented on a reconfigurable gate array to provide an adaptive hardware device suitable for use with a microprocessor.