High-speed scrubbing demonstration using an optically reconfigurable gate array.

Abstract

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs.