Abstract
A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.
Highlights
Field programmable gate arrays (FPGAs) require reconfiguration times of several milliseconds [1], which makes them unsuitable for applications demanding high-speed reconfiguration capabilities. Alternative solutions such as multi-context FPGAs, digital application processors with distributed network architectures (DAPs/DNAs) or dynamic reconfigurable processors (DRPs) have been developed, whose operation is based on incorporating several reconfiguration contexts in specific memory banks
The reconfiguration contexts are stored in the whole 3-D volume of the holographic memory in a page structure, achieving high density, and they are retrieved projecting the information stored in each page on an array of optical detectors, which allows operation at hundreds of megahertz [1,2]
The two laser sources are modulated with the pseudo-random bit sequence (PRBS) generated by a Sympuls BMG-2500 bit pattern generator, and the average power of the modulated light signal is controlled by an optical attenuator before it is fed into the opto-electronic integrated circuit (OEIC) receiver by a multi-mode optical fiber
Summary
Field programmable gate arrays (FPGAs) require reconfiguration times of several milliseconds [1], which makes them unsuitable for applications demanding high-speed reconfiguration capabilities For such applications, alternative solutions such as multi-context FPGAs, digital application processors with distributed network architectures (DAPs/DNAs) or dynamic reconfigurable processors (DRPs) have been developed, whose operation is based on incorporating several reconfiguration contexts in specific memory banks. The circuit is implemented in a 0.35 μm opto-CMOS process fed at 3.3 V and it achieves 400 Mbit/s with a bit error ratio (BER) better than 10−9 for an average input optical power of −26 dBm. The regenerative latch consumes 790 μW, which yields an energy efficiency of. 2 pJ/bit, and, along with the output buffer (excluding the PDs) occupies 50 μm × 30 μm
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