Reconfigurable Field Programmable Gate Array Research Articles

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on static random-access memory (SRAM)-based partially run-time reconfigurable field programmable gate arrays (FPGAs) in harsh environments by taking both single-bit upsets and multiple-cell upsets into account. The model requires some features of the hardware tasks, including their computation time, size, the percent of critical bits, and the soft error rates of k-bit events (k ≥ 1) of the environment for the reliability estimation. Such an early estimation helps the developers to assess the reliability of their designs at earlier stages and leads to reduce the development cost. The proposed model has been evaluated by conducting several experiments on actual hardware tasks over different environmental soft error rates. The obtained results, endorsed by the 95% confidence interval, reveal the high accuracy of the proposed model. When comparing this approach with a reliability model (developed by the authors in a previous work) that does not consider the occurrence of multiple-cell upsets, an overestimation of the mean time to failure of 2.88X is observable in the latter. This points to the importance of taking into account multiple events, especially in modern technologies where the miniaturization is high.

Improved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic Systems

To be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic system under loading conditions and atmospheric data (temperature and irradiance). The goal of this controller is to prove that the FLC is the best technique of MPPT to extract the maximum power of photovoltaic modules. The main objective of this work is the implementation on a “Cyclone II” circuit using “EP2C35F672C6” Development Board reconfigurable Field-Programmable Gate Array (FPGA) with Hardware Description Language (VHDL). Thus, we show the advantages of using the FPGA circuits, which are their short progress time, their low price and their suppleness of process. The close optimum design of this technique is based on the best choice membership functions and control rules for two- input, one-output digital Fuzzy Logic Controller (FLC) based on “Mamdani” mechanism. The simulation and implementation results obtained respectively with waveform under Quartus software and on Cyclone II, both show a satisfactory performance and confirm the good tracking efficacy and speedy response to various atmospheric conditions.

AWARE-CNN: Automated Workflow for Application-Aware Real-Time Edge Acceleration of CNNs

This article presents the application-aware real-time edge acceleration of CNNs (AWARE-CNNs) accelerators, which is a novel architecture design methodology for real-time execution of deep learning algorithms on IoT devices. AWARE leverages the reconfigurability of field-programmable gate arrays (FPGAs) to create application-specific architectures customized to match the inherent dataflow of targeted deep neural networks and user-specified real-time requirements. The customized datapath is combined with a customized memory path to guarantee deterministic latency-aware execution over streaming data. For results and evaluation, we have developed a Chisel-based implementation of AWARE-CNN with a full integrative framework for application-specific architecture generation and synthesis (AWARE-CNN architecture compiler). Our results demonstrate the ability to execute Tiny DarkNet and shallow MobileNet inference at 120 frames/s (FPS) and 75 FPS, using only 2.8 and 3.4 W, respectively, on a Xilinx XCZU9EG FPGA. In addition, AWARE-CNN framework’s flexibility with respect to the targeted convolutional neural networks and user constraints is validated by targeting additional design points for AlexNet (as a baseline network) and Tiny YOLOv2.

Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs

This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces of its reconfigurable modules, the structure of the communications, the inclusion of specialized modules to handle and optimize circuit reconfiguration at runtime, and the organization of the reconfigurable partitions. We evaluate two methods to select the new target partition for modules in faulty partitions and design their hardware as intellectual property modules. We evaluate the performance and scalability of this approach using a trapezoidal shaper, a filter used to detect high-energy particles in radiation experiments, and we carry out the experiments with a variable number of modules and reconfigurable partitions using the two selection algorithms. The proposal is compared with nonfault-tolerant and triple modular redundancy approaches, and it remains functional with up to $12\times $ more injected faults than those.

Software-Defined Radio Transceiver Design Using FPGA-Based System-on-Chip Embedded Platform With Adaptive Digital Predistortion

In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amplifiers (PAs). The implementation of the ADPD on a reconfigurable FPGA platform makes the system flexible and cost-effective. The PA characterization, in terms of model extraction and coefficient calculation, is done in real-time. These calculated coefficients are updated in the transmission path to precondition the transmitted signal before it is applied to the PA. The proposed ADPD is applied at the baseband level. Therefore, it can be used for different classes of PA operating at different RF carrier frequencies. A long-term evolution (LTE) signal with 20 MHz bandwidth and 11 dB peak to average power ratio (PAPR) is used for simulation and measurement purposes. The LTE signal is amplified using a GaN-based harmonically tuned continuous Class-F PA in measurement. The performance of the implemented ADPD scheme is analyzed in terms of NMSE, ACPR and EVM.

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.

Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA

Field programmable gate array (FPGA) that utilizes via-switches, which are a kind of nonvolatile resistive RAMs, for crossbar implementation is attracting attention due to higher integration density and performance. However, programming via-switches arbitrarily in a crossbar is not trivial since a programming current must be provided through signal wires shared by multiple via-switches. Consequently, depending on the previous programming status in sequential programming, unintentional switch programming may occur due to signal detour, which is called the sneak path problem. This article identifies the circuit status that causes the sneak path problem and proposes a sneak path avoidance method that gives sneak path free programming order of via-switches in a crossbar. We prove that sneak path free programming order necessarily exists for arbitrary ON-OFF patterns in a crossbar as long as no loops exist. This article also proposes a partial reconfiguration method that achieves the minimum number of switch programming steps while avoiding the sneak path problem. This method contributes to the extension of via-switch lifetime and fast reconfiguration of the via-switch FPGA. Experimental results show that the proposed partial reconfiguration method reduces the number of programmed switches by 77.4% compared to the conventional approach. This 77.4% reduction improves the number of reconfigurations of the via-switch FPGA by 4.4× and reduces reconfiguration time by 77.4%.

Fault location estimation for series-compensated double-circuit transmission line using EWT and weighted RVFLN

In this paper, empirical Wavelet transform (EWT), Hilbert transform (HT) and weighted random vector functional link network (WRVFLN) are integrated for fault detection, classification, and location estimation in a series capacitor compensated double circuit transmission line (SCCDCTL). The full cycle current signals from the point of fault inception are decomposed using EWT to extract three band-limited modes (BLMs). The four efficacious instantaneous features namely energy, Shannon entropy, the standard deviation of the magnitude, and crest factor are computed from the Hilbert transformed array of the BLMs to construct the feature vector. A diagonal matrix W is computed from the zero sequence current of original six current signals as a weighting factor to categorize the ground fault accurately. Numerous faults are generated with a wide variation of the system conditions such as fault resistance, fault inception angle, fault distance, percentage compensation level, source impedance, line parameters, load angle, and inter-circuit fault in MATLAB/Simulink environments. An efficient WRVFLN computational intelligence technique is proposed to recognize and estimate the location of the faults by taking the extracted suitable feature vector with weight factor as an input. The performances of WRVFLN are compared with the recently developed advanced classifiers such as least-square support vector machine (LSSVM) and extreme learning machine (ELM) in the MATLAB interface. The lesser computational complexity, faster learning speed, superior classification accuracy, accurate fault location estimation, and short event detection time prove that the proposed EWTHT–WRVFLN method can be implemented in the real power system for online fault diagnosis. Finally, the developed system architecture is implemented on the reconfigurable digital field programmable gate array (FPGA) in ISE design suite 14.5 environments to verify the cogency of the proposed method in real-time. The feasibility of the proposed method is tested and validated by using the fast FPGA digital circuitry in a loop.

OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

Field-programmable gate array (FPGA) provides rich parallel computing resources with high energy efficiency, making it ideal for deep convolutional neural network (CNN) acceleration. In recent years, automatic compilers have been developed to generate network-specific FPGA accelerators. However, with more cascading deep CNN algorithms adapted by various complicated tasks, reconfiguration of FPGA devices during runtime becomes unavoidable when network-specific accelerators are employed. Such reconfiguration can be difficult for edge devices. Moreover, network-specific accelerator means regeneration of RTL code and physical implementation whenever the network is updated. This is not easy for CNN end users. In this article, we propose a domain-specific FPGA overlay processor, named OPU to accelerate CNN networks. It offers software-like programmability for CNN end users, as CNN algorithms are automatically compiled into executable codes, which are loaded and executed by OPU without reconfiguration of FPGA for switch or update of CNN networks. Our OPU instructions have complicated functions with variable runtimes but a uniform length. The granularity of instruction is optimized to provide good performance and sufficient flexibility, while reducing complexity to develop microarchitecture and compiler. Experiments show that OPU can achieve an average of 91% runtime multiplication and accumulation unit (MAC) efficiency (RME) among nine different networks. Moreover, for VGG and YOLO networks, OPU outperforms automatically compiled network-specific accelerators in the literature. In addition, OPU shows $5.35\times $ better power efficiency compared with Titan Xp. For a real-time cascaded CNN networks scenario, OPU is $2.9\times $ faster compared with edge computing GPU Jetson Tx2, which has a similar amount of computing resources.

DWT Based Image Steganography with Seven Segment Display Pattern as a Key

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.

Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware

An important aspect of mixed critical systems is to execute tasks of varied criticality on the same platform. The property of full or partial reconfiguration at runtime of reconfigurable hardware or field programmable gate arrays (FPGAs) has satisfied this criterion and facilitated the processing of mixed critical tasks directly on hardware, with the aid of reconfigurable intellectual properties (IPs) or bitstreams procured from various third party IP (3PIP) vendors. However, the existing literature in this arena does not consider the associated hardware threats. Such threats are particularly dangerous as related malware like Hardware Trojan Horses (HTHs) remain dormant during testing and evade detection, but get activated at runtime and jeopardize mission critical applications. Though several works exist on hardware security, none focus on reliability driven mixed critical task processing on reconfigurable hardware against HTH attacks. In this work, we initially explore how HTHs implanted by 3PIP vendors in the bitstreams may cause active attacks. Then, we develop strategies to ensure reliability for processing of mixed critical tasks on reconfigurable hardware. Both periodic and non-periodic, i.e. aperiodic or sporadic tasks are considered. We also focus on resource constrained environments, where we adhere to frequency scaling to facilitate accommodation of tasks on limited resources. We experiment with a variety of bitstreams and performance evaluation is performed via metrics such as task success rate, task rejection rate and task preemption rate.

A multifunction digital receiver suitable for real-time frequency detection and compensation in fast magnetic resonance imaging.

We describe the development and implementation of a multifunction digital receiver suitable for magnetic resonance imaging with capability of real-time frequency detection and compensation. The digital receiver consists primarily of firmware modules that combine the functionalities of signal acquisition, frequency detection and compensation, and data correction and image reconstruction. The receiver was developed based on a single multiple-input multiple-output radio-frequency electronic board equipped with a reconfigurable Field Programmable Gate Array (FPGA) device. A simple and practical algorithm was developed and implemented on the FPGA to accelerate the data processing for frequency determination. The simplified frequency detection and the higher system integration enable the receiver to reduce dramatically the time for frequency detection and compensation. With this receiver, we are able to detect the frequency of short-duration signals in the bandwidth of 10 MHz centered at 400 MHz within 75 ns after the signal acquisition. We describe the designs of the key FPGA modules and how these modules integrate into a multifunction receiver. We also present testing data that validate the simplified algorithm for frequency determination, demonstrate frequency detection and compensation, and demonstrate how real-time data correction is performed during image acquisition and reconstruction.

Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

Exploiting modification direction (EMD)-based image steganography algorithm has higher embedding efficiency, low distortion, and best security that finds application in secure communication, data protection, access control in digital content distribution, etc., EMD steganography encapsulates secret digit represented in (2n + 1)-ary notational system by increasing or decreasing one of the n cover pixels by one. New high-speed reconfigurable architectures and field programmable gate array (FPGA) implementation of EMD based image steganography algorithms have been proposed. Although, earlier work on FPGA implementation of steganography algorithms offer higher speed, low chip area, and better throughput it usually operates on a fixed number of pixels. The proposed system works well for both arbitrary numbers of pixel groups and variable image resolution. The developed system is capable of embedding a secret message from two to eight-pixel groups with an image resolution of 512 × 512 pixels at a real-time video rate of 549 frames/s.. The complete design is implemented using RTL compliant Verilog code which fits into a single FPGA/ASIC chip with a gate density of two million gates.

Design of Reconfigurable SDR Platform for Antenna Selection Aided MIMO Communication System

In recent years, antenna selection (AS) has become one of the most popular research topics for massive multiple-input multiple-output (MIMO) system due to its capability of reducing the number of radio frequency chains utilized for MIMO communications, while remaining the MIMO advantages, such as increased bandwidth efficiency and reliability. In this paper, an efficient norm-based AS (NBAS) algorithm is investigated and implemented in the software defined radio (SDR) MIMO communication platform, which consists of field-programmable gate arrays (FPGAs). Owing to the high freedom and fast reconfigurable FPGA hardware, the SDR MIMO communication platform is capable of developing prototype of NBAS-aided MIMO system. More specifically, the implemented NBAS aided SDR MIMO system is capable of achieving uplink communication from users to the base station via time division duplex (TDD). A time-varying fading channel generation model is designed for SDR MIMO platform to enrich our experimental results. Additionally, a novel multiplexer (MUX) circuit module is designed and implemented to enhance the hardware performance of the FPGA in term of delay and resource usage. More specifically, the Results show that by implementing the low-complexity NBAS, the channel capacity performance of the SDR MIMO system may be significantly improved by around 15%. It is also showed that our proposed optimized MUX circuit intellectual property may reduce the critical path delay by about 2:16 ns, and save at lease 3% hardware resources in SDR FPGA.

On-Line Reusing-Based Scheduling Algorithm for 2-Dimensional Tasks in Reconfigurable Hardware

Reducing reconfiguration overhead is one of the main topics in increasing speed and performance of dynamically reconfigurable Field-Programmable Gate Arrays (FPGA). In this paper, an approach for reusing a repetitive hardware task in 2-dimensional hardware is proposed. At first, incoming tasks are divided into significant and non-significant tasks based on their features. Each group is placed in a specific partition of hardware and several methods such as replacement of significant tasks, using empty spaces in other partition or extending the partition border are applied to better use the resources. Conducted experiments show that in repetitive programs, the proposed method has %20.3 less makespan and decides more than 3 times faster than state-of-the-art algorithms in this field.

MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip

Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from different layers are mapped to the same hardware units and working in a multiplexed way. This manner does not take full advantage of reconfigurability and customizability of FPGAs, resulting in a certain degree of computational efficiency degradation. In this paper, we propose a new architecture for FPGA-based CNN accelerator that maps all the layers to their own on-chip units and working concurrently as a pipeline. A comprehensive mapping and optimizing methodology based on establishing roofline model oriented optimization model is proposed, which can achieve maximum resource utilization as well as optimal computational efficiency. Besides, to ease the programming burden, we propose a design framework which can provide a one-stop function for developers to generate the accelerator with our optimizing methodology. We evaluate our proposal by implementing different modern CNN models on Xilinx Zynq-7020 and Virtex-7 690t FPGA platforms. Experimental results show that our implementations can achieve a peak performance of 910.2 GOPS on Virtex-7 690t, and 36.36 GOP/s/W energy efficiency on Zynq-7020, which are superior to the previous approaches.

A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA

In this brief, a novel low-power, low-area nonvolatile (NV) static random access memory (SRAM) that uses a single magnetic tunneling junction for store/restore operation is proposed. The proposed cell is dynamically reconfigurable in the background, which makes it a proper alternative to replace the SRAM cells of conventional field-programmable gate arrays (FPGAs) for the development of NV-FPGAs. The simulation results show that the proposed cell offers $8.8 {\times }$ lower store time, $1.52 {\times }$ ( $1.08 {\times }$ ) lower store-0 (store-1) energy, and $3.54 {\times }$ lower restore energy, in comparison with the recently reported work. In addition, a high loading speed of 1 ns is achieved by using a separately supplied initialization and pulsed overwrite schemes.

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

The exponentially increasing performance of chip multiprocessors (CMPs) predicted by Moore's Law is no longer due to the increasing clock rate of a single CPU core, but on account of the increase of core counts in the CMP. More transistors are integrated within the same footprint area as the technology node shrinks to deliver higher performance. However, this is accompanied by higher power dissipation that usually exceeds the coping capability of inexpensive cooling techniques. This Power Wall prevents the chip from running at full speed with all the devices powered-on. This is known as the dark silicon problem. Another major bottleneck in CMP development is the imbalance between the CPU clock rate and memory access speed. This Memory Wall keeps the CPU from fully utilizing its compute power. To address both the Power and Memory Walls, we propose a monolithic 3D hybrid architecture that consists of a multi-core CPU tier, a fine-grain dynamically reconfigurable (FDR) field-programmable gate array (FPGA) tier, and multiple resistive RAM (RRAM) tiers. The FDR tier is used as an accelerator. It uses the concept of temporal logic folding to localize on-chip communication. The RRAM tiers are connected to the CPU and FDR tiers through an efficient memory interface that takes advantage of the tremendous bandwidth available from monolithic inter-tier vias and hides the latency of large data transfers. We evaluate the architecture on two types of benchmarks: compute-intensive and memory-intensive. We show that the architecture reduces both power and energy significantly at a better performance for both types of applications. Compared to the baseline, our architecture achieves an average of 43.1× and 2.5× speedup on compute-intensive and memory-intensive benchmarks, respectively. The power and energy consumption are reduced by 5.0× and 40.5×, respectively, for compute-intensive applications, and 2.0× and 4.2×, respectively, for memory-intensive applications. This translates to 1745.3× energy-delay product (EDP) improvement for compute-intensive applications and 10.5× for memory-intensive applications.

RETRACTED: An optimized reconfigurable algorithm for FPGA architecture oriented IoT applications

Application Specific Integrated Circuit (ASIC) can facilitate the user with high speed, but a small modification in the algorithm and architecture will lead to more cost in terms of design and development. In contrast Field Programmable Gate Array (FPGA) provides near optimal speed with reconfigurability of algorithm/architecture at any time. From research survey, we come to conclusion that Fast Fourier Transform (FFT) plays critical role in many applications such as Orthogonal Frequency Division Multiplexing (OFDM), image processing application and signal processing application. In this paper, we have developed a reconfigurable FPGA architecture for FFT algorithm. Also, reconfigurable algorithm is proposed to handover the reconfiguration control, so that the datapath can be changed. The proposed reconfigurable FPGA architecture is developed using Verilog and targeted in Altera FPGA boards. The evaluation and comparison of the proposed architecture shows remarkable improvement in terms of throughput, area and power.

FPGA Dynamic and Partial Reconfiguration

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.