Reconfigurable Field Programmable Gate Array Research Articles

Implementation of Deep Learning-Based Automatic Modulation Classifier on FPGA SDR Platform

Intelligent radios collect information by sensing signals within the radio spectrum, and the automatic modulation recognition (AMR) of signals is one of their most challenging tasks. Although the result of a modulation classification based on a deep neural network is better, the training of the neural network requires complicated calculations and expensive hardware. Therefore, in this paper, we propose a master–slave AMR architecture using the reconfigurability of field-programmable gate arrays (FPGAs). First, we discuss the method of building AMR, by using a stack convolution autoencoder (CAE), and analyze the principles of training and classification. Then, on the basis of the radiofrequency network-on-chip architecture, the constraint conditions of AMR in FPGA are proposed from the aspects of computing optimization and memory access optimization. The experimental results not only demonstrated that AMR-based CAEs worked correctly, but also showed that AMR based on neural networks could be implemented on FPGAs, with the potential for dynamic spectrum allocation and cognitive radio systems.

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators

System accelerators (ACCs) improve performance and break power and utilization walls. They can be implemented by fixed-function hard macros or reconfigurable logic such as field-programmable gate arrays (FPGAs). For systems running various applications, dynamic reconfigurable ACCs offer a very attractive feature; however, the reconfiguration time is an unavoidable overhead. This paper proposes high-performance architecture with fast dynamic reconfigurable FPGA ACCs (F-RACCs) based on a novel bitstream reprogramming method, which is feasible by using emerging technologies. The architecture includes CPU cores, caches, memories, ACCs, and network-on-chips. A portion of the computing tasks can be offloaded from CPUs to ACCs to improve performance. The ACCs can be reprogrammed rapidly to accommodate various functions required by wide spectrum of applications. The performance is evaluated by platform for ACC-rich architectural design and exploration, a gem5-based cycle-accurate full-system simulation platform. The 11 benchmark applications from different domains are evaluated. Comparing with systems using conventional FPGA ACCs partially configured using fastest configuration speed; this architecture improves system performance on all applications and achieves maximum $1.31\times $ and $2.82\times $ speedup using 1 and 12 ACC instances, respectively. It achieves maximum speedup of $94.93\times $ with one and $565.12\times $ with 12 F-RACCs over CPU software path with no ACCs.

Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs

To improve computing performance in real-time applications, modern embedded platforms comprise hardware accelerators that speed up the task’s most compute-intensive parts. A recent trend in the design of real-time embedded systems is to integrate field-programmable gate arrays (FPGA) that are reconfigured with different accelerators at runtime, to cope with dynamic workloads that are subject to timing constraints. One of the major limitations when dealing with partial FPGA reconfiguration in real-time systems is that the reconfiguration port can only perform one reconfiguration at a time: if a high-priority task issues a reconfiguration request while the reconfiguration port is already occupied by a lower-priority task, the high-priority task has to wait until the current reconfiguration is completed (a phenomenon known as priority inversion ), unless the current reconfiguration is aborted (introducing unbounded delays in low-priority tasks, a phenomenon known as starvation ). This article shows how priority inversion and starvation can be solved by making the reconfiguration process preemptive —that is, allowing it to be interrupted at any time and resumed at a later time without restarting it from scratch. Such a feature is crucial for the design of runtime reconfigurable real-time systems but not yet available in today’s platforms. Furthermore, the trade-off of achieving a guaranteed bound on the reconfiguration delay for low-priority tasks and the maximum delay induced for high-priority tasks when preempting an ongoing reconfiguration has been identified and analyzed. Experimental results on the Xilinx Zynq-7000 platform show that the proposed implementation of preemptive reconfiguration introduces a low runtime overhead, thus effectively solving priority inversion and starvation.

Bioelectronic organ-based sensor for microfluidic real-time analysis of the demand in insulin

On-line and real-time analysis of micro-organ activity permits to use the endogenous analytical power of cellular signal transduction algorithms as biosensors. We have developed here such a sensor using only a few pancreatic endocrine islets and the avoidance of transgenes or chemical probes reduces bias and procures general usage. Nutrient and hormone-induced changes in islet ion fluxes through channels provide the first integrative read-out of micro-organ activity. Using extracellular electrodes we captured this read-out non-invasively as slow potentials which reflect glucose concentration-dependent (3–15 mM) micro-organ activation and coupling. Custom-made PDMS-based microfluidics with platinum black micro-electrode arrays required only some tens of islets and functioned at flow rates of 1–10 µl/min which are compatible with microdialysis. We developed hardware solutions for on-line real-time analysis on a reconfigurable Field-Programmable Gate Array (FPGA) that offered resource-efficient architecture and storage of intermediary processing stages. Moreover, real-time adaptive and reconfigurable algorithms accounted for signal disparities and noise distribution. Based on islet slow potentials, this integrated set-up allowed within less than 40 μs the discrimination and precise automatic ranking of small increases (2 mM steps) of glucose concentrations in real time and within the physiological glucose range. This approach shall permit further development in continuous monitoring of the demand for insulin in type 1 diabetes as well as monitoring of organs-on-chip or maturation of stem-cell derived islets.

FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems

SoCs and chip multi processors (CMPs) usually employ a scalable interconnection network (Network-on-chip or NoC) as a communication medium. Existing simulators that can simulate such systems are mostly SW based and as such are very slow. Fast FPGA-based hardware simulators of CMP systems are gaining popularity because they allow fast and efficient exploration of several design points with multiple benchmarks. This entail emulating the NoC in these systems with different parameters and configurations. Existing hardware NoC simulators that are implemented on Field Programmable Gate Arrays (FPGAs) are not readily integrate-able with other FPGA-based multicore architectural simulators. In this work, a new FPGA-based NoC emulator (FBNoC) that can be integrated with multicore architectural simulators is proposed. It can also be used as a standalone NoC simulator. Utilizing a parametrizable latency model, FBNoC can deliver packets and accurately estimate their latencies for several NoC topologies, configurations, and parameters without the need for re-synthesize nor FPGA re-configuration. It also employs a novel multi-local port per NoC node strategy combined with two bidirectional ring networks to reduce the FPGA resource utilization while increasing the simulation speed. Requiring less FPGA resources than other FPGA-based NoC simulators, the proposed emulator can achieve more than 20,000x speedup over the popular SW NoC simulator Booksim.

A New Method of Recording Generator Dynamics and Its Application to the Derivation of Synchronous Machine Parameters for Power System Stability Studies

The proposed algorithm is based on the discrete Fourier transform (DFT) and a software-based synchronous sampling technique that is locked to the power system frequency using reconfigurable field-programmable gate arrays (FPGAs). The main purposes of this paper are to provide a new method of recording the high-resolution rotor angle of a synchronous machine and a practical method for deriving more accurate d-q- axis synchronous machine parameters. An FPGA is used in realizing the rotor-angle transducer and it simultaneously detects the frequency of the generator terminal voltage. The DFT algorithm is combined with an interpolation technique that downsamples the high-frequency sampled data using the measured power system frequency. This paper also describes a practical method for determining synchronous machine model parameters. The proposed algorithm for recording the generator dynamics was implemented in terms of Labview, Real-Time PCI eXtensions for Instrumentation (PXI) target, and the FPGA, and was applied to generator testing of a 1205-MVA thermal power unit. Its synchronous machine parameters were also derived using the recorded rotor angle.

FPGA Implementation of the CCSDS 1.2.3 Standard for Real-Time Hyperspectral Lossless Compression

Hyperspectral images taken by satellites pose a challenge for data transmission. Communication with Earth's antennas is usually time restricted and bandwidth is very limited. The CCSDS 1.2.3 algorithm mitigates this issue by defining a lossless compression standard for this kind of data, allowing more efficient usage of the transmission link. Reconfigurable field-programmable gate arrays (FPGAs) are promising platforms that provide powerful on-board computing capabilities and flexibility at the same time. In this paper, we present an FPGA implementation for the CCSDS 1.2.3 algorithm. The proposed method has been implemented on the Virtex-4 XC2VFX60 FPGA (the commercial equivalent of the space-qualified Virtex-4QV XQR4VF60 FPGA) and on the Virtex-7 XC7VX690T, and tested using real hyperspectral data collected by NASA's airborne visible infra-red imaging spectrometer (AVIRIS) and two procedurally generated synthetic images. Our design, occupying a mere third of the Virtex-4 XC2VFX60 FPGA, has a very low power consumption and achieves real-time compression for hyperspectral imaging devices such as NASA's NG-AVIRIS. For this, we use the board's memory as a cache for input data, which allows us to process images as streams of data, completely eliminating storage needs. All these factors make it a great option for on-satellite compression.

A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering

Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, fieldprogrammable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales as O(ω <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) with the filter width ω. In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just O(1) operations for any arbitrary ω. The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.

Three-dimensional artificial organism model developed upon a two-layer coarse-fine-grid network approach

In an attempt to devise a model which more closely imitates cellular biology a three-dimensional (3D) artificial organism model developed upon a two-layer coarse-fine-grid network model is proposed in this paper. The strength of this original approach is that it endeavors to capture the complexity of both the cellular networks as well as that of the biological cell itself, by implementing the internal biological phenomena of an organism into a 3D two different network topology hardware layer. In essence, this model not only keeps the full advantages of previously created 2D models that enable the implementation of similar self-replicating or selfrepairing abilities akin to those expressed by its cellular equivalents in nature, but there the inherent need of artificial cell structures to fulfill the entire role of a biological cell in the network is also expressed. Computer-aided simulation results prove that this kind of 3D coarse-fine-grid approach is well feasible physically therefore the model has been implemented into a computing platform made of custom reconfigurable Field Programmable Gate Array (FPGA) processors.

Investigation of FPGA-Based Real-Time Adaptive Digital Pulse Shaping for High-Count-Rate Applications

Digital signal processing techniques have been widely used in radiation spectrometry to provide improved stability and performance with compact physical size over the traditional analog signal processing. In this paper, field-programmable gate array (FPGA)-based adaptive digital pulse shaping techniques are investigated for real-time signal processing. National Instruments (NI) NI 5761 14-bit, 250-MS/s adaptor module is used for digitizing high-purity germanium (HPGe) detector’s preamplifier pulses. Digital pulse processing algorithms are implemented on the NI PXIe-7975R reconfigurable FPGA (Kintex-7) using the LabVIEW FPGA module. Based on the time separation between successive input pulses, the adaptive shaping algorithm selects the optimum shaping parameters (rise time and flattop time of trapezoid-shaping filter) for each incoming signal. A digital Sallen–Key low-pass filter is implemented to enhance signal-to-noise ratio and reduce baseline drifting in trapezoid shaping. A recursive trapezoid-shaping filter algorithm is employed for pole-zero compensation of exponentially decayed (with two-decay constants) preamplifier pulses of an HPGe detector. It allows extraction of pulse height information at the beginning of each pulse, thereby reducing the pulse pileup and increasing throughput. The algorithms for RC–CR2 timing filter, baseline restoration, pile-up rejection, and pulse height determination are digitally implemented for radiation spectroscopy. Traditionally, at high-count-rate conditions, a shorter shaping time is preferred to achieve high throughput, which deteriorates energy resolution. In this paper, experimental results are presented for varying count-rate and pulse shaping conditions. Using adaptive shaping, increased throughput is accepted while preserving the energy resolution observed using the longer shaping times.

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

SummaryThe vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

Radiation effects in reconfigurable FPGAs

Field-programmable gate arrays (FPGAs) are co-processing hardware used in image and signal processing. FPGA are programmed with custom implementations of an algorithm. These algorithms are highly parallel hardware designs that are faster than software implementations. This flexibility and speed has made FPGAs attractive for many space programs that need in situ, high-speed signal processing for data categorization and data compression. Most commercial FPGAs are affected by the space radiation environment, though. Problems with TID has restricted the use of flash-based FPGAs. Static random access memory based FPGAs must be mitigated to suppress errors from single-event upsets. This paper provides a review of radiation effects issues in reconfigurable FPGAs and discusses methods for mitigating these problems. With careful design it is possible to use these components effectively and resiliently.

FPGA Implementation of SVM for Nonlinear Systems Regression

This work resumes the previous implementations of Support Vector Machine for Classification and Regression and explicates the different methods and approaches adopted. Ever since the rarity of works in the field of nonlinear systems regression, an implementation of testing phase of SVM was proposed exploiting the parallelism and reconfigurability of Field-Programmable Gate Arrays (FPGA) platform. The nonlinear system chosen for application was a real challenging model: a fluid level control system existing in our laboratory. The implemented design with fixed point precision demonstrates good enough results comparing with the software performances based on the Normalized Mean Squared Error. Whereas, in term of computation time, a speed-up factor of 60 orders of time comparing to MATLAB results was achieved. Due to the flexibility of Xilinx System Generator, the design is capable to be reused for any other system with different data sets sizes and various kernel functions.

FPGA Implementation of an Algorithm for Automatically Detecting Targets in Remotely Sensed Hyperspectral Images

Timely detection of targets continues to be a relevant challenge for hyperspectral remote sensing capability. The automatic target-generation process using an orthogonal projection operator (ATGP-OSP) has been widely used for this purpose. Hyperspectral target-detection applications require timely responses for swift decisions, which depend upon (near) real-time performance of algorithm analysis. Reconfigurable field-programmable gate arrays (FPGAs) are promising platforms that allow hardware/software codesign and the potential to provide powerful onboard computing capabilities and flexibility at the same time. In this paper, we present an FPGA implementation for the ATGP-OSP algorithm. Our system includes a direct memory access module and implements a prefetching technique to hide the latency of the input/output communications. The proposed method has been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that our hardware version of the ATGP-OSP algorithm can significantly outperform a software version, which makes our reconfigurable system appealing for onboard hyperspectral data processing.

Leveraging FPGAs for Accelerating Short Read Alignment.

One of the key challenges facing genomics today is how to efficiently analyze the massive amounts of data produced by next-generation sequencing platforms. With general-purpose computing systems struggling to address this challenge, specialized processors such as the Field-Programmable Gate Array (FPGA) are receiving growing interest. The means by which to leverage this technology for accelerating genomic data analysis is however largely unexplored. In this paper, we present a runtime reconfigurable architecture for accelerating short read alignment using FPGAs. This architecture exploits the reconfigurability of FPGAs to allow the development of fast yet flexible alignment designs. We apply this architecture to develop an alignment design which supports exact and approximate alignment with up to two mismatches. Our design is based on the FM-index, with optimizations to improve the alignment performance. In particular, the n-step FM-index, index oversampling, a seed-and-compare stage, and bi-directional backtracking are included. Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs. Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5-2640 CPUs, and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU.

Runtime Reconfiguration of FPGA for Biomedical Applications

This paper describes the usage of Field Programmable Gate Array (FPGA) to explore reconfiguration to help out in the field of Biomedical Applications. The FPGA is reconfigured at runtime to analyze parameters like temperature, heart rate, blood pressure of patients and identify the conditions as normal, critical or emergency. According to the applications implemented there are two ways used to approach the Dynamic Partial Reconfiguration (DPR) practically. First is to configure the FPGA before reconfiguration and this part is known as static or fixed programming. Next part we reconfigure the FPGA again and run the program this is known as the partial reconfigurable part of the system. Basically initially two nodes are taken a temperature sensor along with the smoke sensor, after reconfiguration two more nodes are incorporated photo detector and Infrared Radiation (IR) sensor. Runtime reconfiguration is done to monitor parameters like blood pressure, heart rate, oxygen saturation etc. The runtime reconfiguration is carried out where we allow the user to enter the patient number and FPGA displays the condition of that particular patient at runtime. Hence a particular patients output can be observed. For which we can have n input patients and we can get the monitored continuous status of the nth patient. Such type of the program can be useful to send data wireless to the doctor and patient can be checked for the particular parameter. The outcomes involve displaying normal condition at temperature 98 °F & respiration rate of 17 inhalations per minute, displaying critical condition at temperature 102 ° F & respiration rate of 30 inhalations per minute, displaying emergency condition at temperature 96 ° F & respiration rate 127 inhalations per minute, emergency condition for the heart rate and the oxygen saturation levels of the patient while the temperature module keeps on function but not displayed. Also displayed is DPR for heart rate 70 bpm and oxygen saturation of 95 % indicates the normal condition, critical condition in DPR for heart rate 35 bpm and oxygen saturation at 85 %, emergency condition in DPR for heart rate 165bpm and oxygen saturation at 60%. Normal condition in DPR for bpl 85 mmHg and bph 120 mmHg. The blood pressure of patient is monitored as normal condition in DPR for bpl 88 mm Hg and bph 108 mm Hg. Normal condition in DPR18 for bpl 94 mmHg and bph 150 mmHg. The above work can be successfully incorporated for patient health monitoring and can be further improved by sending wirelessly the data to a central hub if the patient’s location is at some remote place.

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable field programmable gate array architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx’s commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive application programming interface, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the smallest univalue segment assimilating nucleus image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-the-art prefetching algorithms, with only a minor energy overhead.

A new method of fault tolerance based on partial reconfiguration

When field programmable gate array (FPGA) applied in the space, it is easily subjected to the single event upset (SEU) effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy (TMR) technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the area-delay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by $3.6\times $ compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective area-delay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.