A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA

Abstract

In this brief, a novel low-power, low-area nonvolatile (NV) static random access memory (SRAM) that uses a single magnetic tunneling junction for store/restore operation is proposed. The proposed cell is dynamically reconfigurable in the background, which makes it a proper alternative to replace the SRAM cells of conventional field-programmable gate arrays (FPGAs) for the development of NV-FPGAs. The simulation results show that the proposed cell offers $8.8 {\times }$ lower store time, $1.52 {\times }$ ( $1.08 {\times }$ ) lower store-0 (store-1) energy, and $3.54 {\times }$ lower restore energy, in comparison with the recently reported work. In addition, a high loading speed of 1 ns is achieved by using a separately supplied initialization and pulsed overwrite schemes.