Abstract
Reducing reconfiguration overhead is one of the main topics in increasing speed and performance of dynamically reconfigurable Field-Programmable Gate Arrays (FPGA). In this paper, an approach for reusing a repetitive hardware task in 2-dimensional hardware is proposed. At first, incoming tasks are divided into significant and non-significant tasks based on their features. Each group is placed in a specific partition of hardware and several methods such as replacement of significant tasks, using empty spaces in other partition or extending the partition border are applied to better use the resources. Conducted experiments show that in repetitive programs, the proposed method has %20.3 less makespan and decides more than 3 times faster than state-of-the-art algorithms in this field.
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