Real-time Image Processing Applications Research Articles

Fast pairwise nearest neighbor based algorithm for multilevel thresholding

We propose a fast pairwise nearest neighbor (PNN)- based O(N log N) time algorithm for multilevel nonparametric thresh- olding, where N denotes the size of the image histogram. The pro- posed PNN-based multilevel thresholding algorithm is considerably faster than optimal thresholding. On a set of 8 to 16 bits-per-pixel real images, experimental results also reveal that the proposed method provides better quality than the Lloyd-Max quantizer alone. Since the time complexity of the proposed thresholding algorithm is log linear, it is applicable in real-time image processing applications. © 2003 SPIE and IS&T. (DOI: 10.1117/1.1604396)

Realizations of fast 2-D/3-D image filtering and enhancement.

This paper proposes a novel algorithm for multidimensional image enhancement based on a fuzzy domain enhancement method, and an implementation of a recursive and separable low-pass filter. Considering a smoothed image as a fuzzy data set, each pixel in an image is processed independently, using fuzzy domain transformation and enhancement of both the dynamic range and the local gray level variations. The algorithm has the advantages of being fast and adaptive, so it can be used in real-time image processing applications and for multidimensional data with low computational cost. It also has the ability to reduce noise and unwanted background that may affect the visualization quality of two-dimensional (2-D)/three-dimensional (3-D) data. Examples for the applications of the algorithm are given for mammograms, ultrasound 3-D images, and photographic images.

Optical properties of Bi12SiO20 (BSO) and Bi12TiO20 (BTO) obtained by mechanical alloying

Mechanical alloying has been used successfully to produce nanocrystalline powders of BTO and BSO. The milled BTO and BSO were studied by x-ray powder diffraction, DTA, infrared and Raman scattering spectroscopy. After 7 hours of milling the formation of BTO and BSO was confirmed by x-ray powder diffraction. The infrared and Raman scattering spectroscopy results suggest that the increase of the milling time lead to the formation of ferroelectric BTO and BSO, as seen by x-ray diffraction analysis. These materials are attractive for various electro-optical devices, including optical data processing. They present a number of attractive features as reversible recording materials for real-time holography and image processing applications. This milling process presents the advantage, that melting is not necessary, and the powder obtained is nanocrystalline with extraordinary mechanical properties. The material, can be compacted and transformed in solid piezoelectric ceramic samples. The high efficiency of the process, opens a way to produce commercial amount of nanocrystalline piezoelectric powders. Due to the nanocrystalline character of this powder, their mechanical properties have changed and for this reason a pressure of 1 GPa is enough to shape the sample into any geometry.

Space Application of a Self-Calibrating Optical Processor for Harsh Mechanical Environment

An optical image processing device based on a Joint Transform Optical Correlator provides high processing speed and could be very usable in real-time image processing applications. In harsh mechanical environment the performance of the correlator could degrade due to mechanical deformations of the optical system. With special self-calibration methods the Joint Transform Optical Correlator can be built insensitive to mechanical disturbances.

VLIW DSP - A Scalable, High Performance Digital Processing Platform for Printers and Copiers

Because of their high-speed arithmetic computation and memory access facilities, very long instruction word digital signal processors (VLIW DSPs) are extremely well suited for real-time image processing applications. This paper illustrates how PDLs such as Postscript can be ported from a traditional ASIC based controller environment to a VLIW DSP based environment and elements of the page processing pipeline accelerated using high-speed arithmetic operations coupled with VLIW parallel execution capabilities. The paper also compares and contrasts traditional RISC and ASIC architectures with the emerging RISC and DSP architectures. This new more programmable environment can make interfaces of the system components more modular and flexible which helps a controller developer to reduce system development time and cost and have a easily scalable controller architecture.

A programmable image processor for real-time image processing applications

In this article we present an architectural design and analysis of a programmable image processor, named Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures.

Tools for code optimization and system evaluation of the image processing system PAPRICA-3

Abstract This paper presents the complex environment that was built to ease the prototyping of real-time applications on the PAPRICA-3 massively parallel system. Applications are developed in C++ using high level data types and the corresponding Assembly code is automatically created by a code generator. A stochastic code optimizer takes the assembly code and improves it according to a genetic approach; due to the high computational power required by this approach, the stochastic code optimizer was implemented with MPI and runs in parallel on a cluster of workstations. The availability of this complex environment allowed to test the performance of the system and to tune it according to some target applications before the actual development of the hardware. For this purpose a system-level simulator was also built to determine the number of clock cycles required to run a specific segment of code. The whole environment has been used to validate possible solutions for the hardware system and to develop, test, and tune several real-time image processing applications. The hardware system is now completely defined.

A linear array processor with dynamic frequency clocking for image processing applications

The need for high-performance image processing systems has led to the design and development of several application-specific parallel processing systems. An SIMD linear array processor with dynamic frequency clocking is proposed for real-time image processing applications. The architecture uses a novel concept called dynamic frequency clocking which allows the processor to vary the clock frequency dynamically based on the operation being performed. A VLSI chip based on the proposed architecture has been designed and verified using the Cadence design tools. The chip will operate at between 400 and 50 MHz based on the operation being performed. Several low-level image processing tasks have been mapped onto the architecture to evaluate the system performance and to demonstrate the effectiveness of the dynamic frequency clocking scheme.

EFFICIENT IMAGE PROCESSING APPLICATIONS ON THE MasPar MASSIVELY PARALLEL COMPUTERS

Image processing applications are suitable candidates for parallelism and have at least in part motivated the design and development of some of the pioneering massively parallel processing systems including the CLIP family, the DAP, the MPP and the GAPP. In this paper, we describe the implementation of various image processing algorithms on the MasPar massively parallel computer system. The suitability of the MasPar for solving image processing algorithms is demonstrated either by parallelizing the algorithms using successful known techniques and/or developing new techniques suitable for the MasPar architecture. We quantitatively evaluate the performance of MasPar in solving these problems. Then, we compare its performance to various related massively parallel architectures. It is shown that the MasPar system compares favorably to these architectures, and is able to execute many fundamental image processing applications in a time amenable to real-time processing. Thus, the MasPar seems to be a promising architecture for massively parallel real-time image processing applications.

A VLSI IMPLEMENTATION OF THE INVERSE DISCRETE COSINE TRANSFORM

The Inverse Discrete Cosine Transform (IDCT) is an important function in HDTV, digital TV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the input coefficient sequence and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity suitable for custom implementation in VLSI. This regularity can be exploited, so that a single permutation can be used to derive each output column from the previous one using a circular shift of an accumulator’s input data multiplied in a special sequence. This technique, using only one 1-dimensional IDCT processor and seven constant multipliers, and its implementation are presented. Operation of 58 MHz under worst case conditions is easily achieved, thus making the design applicable to a wide range of video and real time image processing applications. Fabricated in 0.5 micron triple metal CMOS technology, the IDCT contains 70,000 transistors occupying 7 mm2 square silicon. The design has been used on an AT&T MPEG video decoder chip.

Functional programming on a dataflow architecture: Applications in real-time image processing

This paper presents a dataflow functional computer (DFFC) developed at the Etablissement Technique Central de l'Armement (ETCA) and dedicated to real-time image processing. Two types of data-driven processing elements, dedicated respectively to low-level and mid-level processings are integrated in a regular 3D array. The design of the DFFC relies on a close integration of the dataflow-architecture principles and the functional programming concept. An image processing algorithm, expressed with a syntax similar to that of functional programming (FP) is first converted into a dataflow graph. The nodes of this graph are real-time operators that can be implemented on the physical processors of the dataflow machine. This dataflow graph is then mapped directly onto the processor array. The programming environment includes a complete compilation stream from the FP specification to hardware implementation, along with a global operator database. Apart from being a research tool for real-time image processing, the DFFC may also be used to perform the automatic synthesis of autonomous vision automata from a high-level functional specification. An experimental system, including 1024 lowlevel custom dataflow processors and 12 T800 transputers, was built and can perform up to 50 billion operations/s. Several image processing algorithms were implemented on this system and run in real-time at digital video speed.

Modular VLSI architectures for real-time full-search-based vector quantization

Vector quantization (VQ) has become feasible to be employed for real-time applications by using VLSI technology. In this paper, the authors propose modular linearly connected VLSI architectures for VQ that can support real-time image processing applications. Each processing element in the design consists of an adder and a shift register instead of a multiplier. The designs require fixed I/O bandwidth with the host and allow codebook changes. The throughput is independent of the codebook size. These designs can be extended to the case when a fixed number of processors are available. A number of VQ schemes-single-stage and multistage VQ, classified VQ, etc.-can be implemented using this approach. >

A defect-tolerant systolic array implementation for real time image processing

An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of two hundred and fifty-six taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations. >

Fast block implementation of two-dimensional FIR digital filters by systolic arrays

A systolic block implementation is described of two-dimensional (2D) FIR and quarter-plane digital filters. Initially, a general 2D block realization model is presented, which does not assume any restricted relation with respect to the block lengths. A high degree of concurrency is achieved by exploiting the pipelining of the array processors in conjunction with the inherent parallelism of the block realization structures. The resulting systolic implementation is characterized by a high degree of modularity, regularity, repetitiveness and local communications and permits very high sampling rates. The increase of the block lengths of the implementation is analogous to the attained throughput rate, with respect to the cost of supporting hardware. The proposed systolic implementation is suitable for real-time image processing applications.

A structure feature for some image processing applications based on spiral functions

A new low-level vision primitive based on logarithmic spirals is presented for various image processing tasks. The detection of such primitives is equivalent to detection of lines and edges in another coordinate system which has been used to model the mapping of the visual field to the striate cortex. Algorithms detecting the proposed primitives and pointing out a matched subclass are presented along with necessary theory. As a result, if the local structure is describable by the proposed primitives then a certainty parameter based on a well-defined mismatch (error) function will indicate this. Moreover, the best fit of a subclass of the proposed primitives in the least squares sense will be computed. The resulting images are unthresholded. They are computed by means of simple convolutions and pixelwise arithmetic operations which make the algorithms suitable for real time image processing applications. Since the resulting images contain information about the local structure, they can be used as feature images in applications like remote sensing, texture analysis, and object recognition. Experimental results on the latter including synthetic as well as natural images are presented along with noise sensitivity tests. The results exhibit good detection properties for the subclasses of the modelled primitives along with uniform and reliable behavior of the corresponding certainty measures.

Image processing enhancement of high-resolution TEM micrographs of nanometer-size metal particles

The high-resolution TEM detectability of lattice fringes from metal particles supported on substrates is impeded by the substrate itself. This effect appears in both amorphous and crystalline substrates. In the former case, it is due to substrate-generated phase contrast features; in the latter case it is due to the intermixing of fringes from particle and substrate. Single value decomposition (SVD) and Fourier filtering (FFT) methods were applied to standard high resolution micrographs to enhance lattice resolution from particles as well as from crystalline substrates. SVD produced good results for one direction of fringes, and it can be implemented as a real-time process. Fourier methods are independent of azimuthal directions and allow separation of particle lattice planes from those pertaining to the substrate, which makes it feasible to detect possible substrate distortions produced by the supported particle. This method, on the other hand, is more elaborate, requires more computer time than SVD and is, therefore, less likely to be used in real-time image processing applications.

Minimum cycle fast implementation of two-dimensional digital filters based on the LU decomposition

A new architecture for two-dimensional filters is presented, which is based on the LU matrix decomposition and is characterized by minimum cycle time. The clock cycle time in the proposed structure is determined by one multiplication and three additions, which are the maximum number of arithmetic operations in the critical path, independently of the filter's order. This realization is characterized by all known advantages of decomposition structures (modularity, parallelism, reconfigurability) and may be used in real-time image processing applications.

Analysis Of Binarized Hartley Phase-Only-Filter Performance With Respect To Stochastic Noise

Binary phase-only filters (BPOFs) are a viable candidate for the replacement of matched filters in real-time image processing and pattern recognition applications. The original BPOFs were binarized versions of the real or imaginary parts of the Fourier transform. Recently, a filter has been proposed that is the binarized Hartley transform. In this paper, the noise performance of the binarized Hartley phase-only filter is analyzed and compared with other BPOFs as well as with the phase-only and matched filters. It is well known that the matched filter optimizes the signal-to-noise ratio. Further, it can be shown that the matched filter phase is the optimum phase-only filter. A bound on the BPOF signal-to-noise ratio relative to that of the phase-only filter is derived. Finally, the analysis is applied to the generalized form of the binarized Hartley transform.

Modular architectures for two-dimensional digital signal processing

The implementation of highly modular two-dimensional (2-D) digital filters is addressed. The idea of matrix decomposition is used to provide increased parallelism and regularity. Four different structures, namely, the transversal, the distributed arithmetic, the stored product, and the systolic array, are considered. For comparison purposes, the direct implementation is included. An analysis of each of each is performed and comparisons are made in terms of hardware cost, cycle time, finite register length effects, and regularity. It is found that the systolic array structure seems to offer the best compromise among the various conflicting figures of merit. The distributed arithmetic structure is shown to be superior in the case of low-order filters, while the stored product structure is preferable for high-order filters. The inherent parallelism and high throughput rate of these structures make them suitable for real-time image processing applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

3 μm VLSI processing element using the CORDIC algorithm

A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor has been designed in 3 μm CMOS technology such that when organised in a pipeline array it can achieve computation rates equivalent to 50 ns, suitable for most real-time signal and image processing applications.