Real-time Image Processing Applications Research Articles

Performance evaluation of an automotive distributed architecture based on a high speed power line communication protocol using a transaction level modeling approach

With the increasing complexity of communication infrastructures in the automotive domain, approaches for modeling architectures at a high abstraction level have become mandatory to assist designers in the development process of such networked embedded systems. Simulation of architecture models, early in the design process, is also necessary to detect and fix errors and performance issues. In this context, transaction level modeling approaches, supported by languages like SystemC, represent promising solutions to allow performances of networked architectures to be assessed with a good compromise between accuracy and simulation speed. This article presents the application of a simulation-based approach for performance evaluation of a networked embedded system inspired by the automotive domain. The presented modeling approach is defined to efficiently capture the characteristics of architectures for real-time image processing applications. The originality of this paper concerns the considered case study which corresponds to the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. Compared with traditional communication protocols used in the automotive domain, power line communication is considered here to improve integration of advanced real-time image processing applications. The created model incorporates the description of the different communication layers involved in the studied distributed architecture. Simulation of the model allows evaluating time properties of the architecture according to the various system parameters. Furthermore, the memory cost inferred is also evaluated. Architecture parameters can then be correctly tuned to fully meet the expected requirements.

Software architecture for time-constrained machine vision applications

Real-time image and video processing applications require skilled architects, and recent trends in the hardware platform make the design and implementation of these applications increasingly complex. Many frameworks and libraries have been proposed or commercialized to simplify the design and tuning of real-time image processing applications. However, they tend to lack flexibility, because they are normally oriented toward particular types of applications, or they impose specific data processing models such as the pipeline. Other issues include large memory footprints, difficulty for reuse, and inefficient execution on multicore processors. We present a novel software architecture for time-constrained machine vision applications that addresses these issues. The architecture is divided into three layers. The platform abstraction layer provides a high-level application programming interface for the rest of the architecture. The messaging layer provides a message-passing interface based on a dynamic publish/subscribe pattern. A topic-based filtering in which messages are published to topics is used to route the messages from the publishers to the subscribers interested in a particular type of message. The application layer provides a repository for reusable application modules designed for machine vision applications. These modules, which include acquisition, visualization, communication, user interface, and data processing, take advantage of the power of well-known libraries such as OpenCV, Intel IPP, or CUDA. Finally, the proposed architecture is applied to a real machine vision application: a jam detector for steel pickling lines.

Fuzzy Logic based Adaptive Noise Filter for Real Time Image Processing Applications

In this paper we implement a new technique for detection and removal of impulse noise from the grayscale digital images. Proposed method consist of the three steps, in the first step, center pixel of the window is tested whether impulse noise is present or not, detected pixel has impulse noise when it lies outside from the trimming range by using fuzzy reasoning. In the second step, we replace the noisy pixels by using median filters. In third stage we create a histogram if the image and again remove the noise by using soft thresholding. The results of the proposed technique for the removal and detection of impulse noise from the gray scale images is very good rather than exiting technique in terms of PSNR values.

Image and video processing platform for field programmable gate arrays using a high-level synthesis

In this study, an image and video processing platform (IVPP) based on field programmable gate array (FPGAs) is presented. This hardware/software co-design platform has been implemented on a Xilinx Virtex-5 FPGA using a high-level synthesis and can be used to realise and test complex algorithms for real-time image and video processing applications. The video interface blocks are done in Register Transfer Languages and can be configured using the MicroBlaze processor allowing the support of multiple video resolutions. The IVPP provides the required logic to easily plug-in the generated processing blocks without modifying the front-end (capturing video data) and the back-end (displaying processed output data). The IVPP can be a complete hardware solution for a broad range of real-time image/video processing applications including video encoding/decoding, surveillance, detection and recognition.

Matrix decomposition graphics processing unit solver for Poisson image editing

In recent years, gradient-domain methods have been widely discussed in the image processing field, including seamless cloning and image stitching. These algorithms are commonly carried out by solving a large sparse linear system: the Poisson equation. However, solving the Poisson equation is a computational and memory intensive task which makes it not suitable for real-time image editing. A new matrix decomposition graphics processing unit (GPU) solver (MDGS) is proposed to settle the problem. A matrix decomposition method is used to distribute the work among GPU threads, so that MDGS will take full advantage of the computing power of current GPUs. Additionally, MDGS is a hybrid solver (combines both the direct and iterative techniques) and has two-level architecture. These enable MDGS to generate identical solutions with those of the common Poisson methods and achieve high convergence rate in most cases. This approach is advantageous in terms of parallelizability, enabling real-time image processing, low memory-taken and extensive applications.

Fuzzy diffusion filter with extended neighborhood

Anisotropic diffusion filters, which are motivated from heat diffusion between mediums, have become a widely used technique in the field of image processing. In the initial proposals of anisotropic diffusion filters, 4-neighborhood values with diffusivity functions are computed independently for each spatial location because of numerical approximation. However, anisotropic diffusion filters could not be used in real-time image and video processing applications because they need diffusivity parameters, which must be specified by users in every sampling period. In this study, a fuzzy adaptive diffusion filter using extended neighborhood without diffusivity functions has been developed. The fuzzy adaptive diffusion filter does not require any parameter chosen by user and therefore they could be employed in real-time applications. In the fuzzy adaptive diffusion filter, a similarity transformation by means of relation matrix and fuzzy logic is carried out. Accordingly, the similarity image, output of transformation, is directly used as a heat diffusion coefficient in the diffusion filter. Results show that the fuzzy adaptive diffusion filter is very efficient for removing noise in image while preserving edges.

Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better.

Hardware Description of Multi-Directional Fast Sobel Edge Detection Processor by VHDL for Implementing on FPGA

The VHDL is an appropriate Hardware Description Language (HDL) for providing hardware models of practical image processing algorithms. The aim of this paper is to present hardware architecture of Sobel edge detection algorithm for implementing on field programmable gate array (FPGA) chips. The proposed architecture calculates the edges of gray scale images in four directions; vertical, horizontal, right diagonal and left diagonal. Simulation results and synthesizing proposed Sobel edge detection processor on Xilinx Spartan3 XC3S200 FPGA chip demonstrate the efficiency of proposed architecture for edge detecting of gray scale 1024×1024 images for real-time image processing applications. General Terms FPGA, Application Specific Processors, Image Processing.

EDLines: A real-time line segment detector with a false detection control

We propose a linear time line segment detector that gives accurate results, requires no parameter tuning, and runs up to 11 times faster than the fastest known line segment detector in the literature; namely, the line segment detector (LSD) by Grompone von Gioi et al. The proposed algorithm makes use of the clean, contiguous (connected) chain of edge pixels produced by our novel edge detector, the Edge Drawing ( ED) algorithm; hence the name EDLines. The detector includes a line validation step due to the Helmholtz principle, which lets it control the number of false detections. With its accurate results and blazing speed, EDLines will be very suitable for the next generation real-time computer vision and image processing applications.

Special issue on parallel computing for real-time image processing

The performance requirements of image processing applications have continuously increased, especially when they are executed under real-time constraints. We have organized this special issue on parallel computing for real-time image processing to present the current state-of-the-art in the field of parallel programming and the future trends in real-time image and video processing as related to parallel computing or real-time implementation of embedded image processing applications on parallel architectures including multi-core platforms, GPUs and dedicated parallel architectures. Due to the overwhelming number and their wide scope of submissions received for this special issue and thus the difficulty associated with finding expert reviewers, we have decided to offer this special issue in two or possibly three parts to meet the planned appearance of this special issue. The papers that are currently under review will appear in a second or a third part of this special issue immediately after their reviews and re-reviews are concluded. We are very grateful to the reviewers who provided valuable comments and suggestions to improve the quality of the accepted papers. This first part of the special issue on parallel computing for real-time image processing presents articles addressing GPU/Multi-GPU programming and is dedicated to parallel architectures based on FPGA and/or CMOS VLSI technologies for real-time image processing applications. Six papers appear in this first part. Brief outlines of these papers are stated below: The first paper by Anis Rahman, Dominique Houzet, Denis Pellerin, Sophie Marat and Nathalie Guyader describes a parallel implementation of a spatio-temporal visual saliency model with multi-GPU reaching a real-time throughput. This article focuses on the algorithms of this model and details several parallel optimizations. The second paper by Fernanda Palhano, Guillermo Andrade-Barroso and Pierre Hellier presents a method for real-time denoising of ultrasound images discussing a modified version of the NL-means method that incorporates an ultrasound dedicated noise model. It addresses a GPU implementation of this algorithm. Results demonstrate that the proposed method is quite efficient in terms of denoising quality and real-time performance. The third paper by Harald Jordan, Walter van Dyck and Rene Smodic describes a new approach for a contourtracking algorithm targeting a low power smart camera for industrial inspection. This embedded system consists of the three major components: CMOS sensor, FPGA and microprocessor. The fourth paper by Mathieu Thevenin, Michel Paindavoine, Laurent Letellier, Renaud Schmit, and Barthelemy Heyrman describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than $1 mm and 500 mW in TSMC 65 nm technology). The fifth paper by Loic Sieler, Lionel Damez, Landrault Alexis and Jean-Pierre Derutin presents the parallelization and the embedding of a real-time image stabilization algorithm on SoPC platform. The overall hardware implementation method is based upon meeting algorithm M. Akil (&) L. Perroton Universite Paris-Est, LIGM, Equipe A3SI, ESIEE Paris Cite Descartes, BP 99, 93162 Noisy-le-Grand Cedex, France e-mail: akilm@esiee.fr

Performance Evaluation of Squaring Operation by Vedic Mathematics

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with a small computational time (delay). As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time; therefore, it becomes imperative to concentrate on improving the speed with which we square the numbers. The squaring operation also forms the backbone in cryptography. In this paper, we propose a technique for implementing squaring operation using Vedic methods in VHDL and evaluate the performance. The results are compared with the conventional Booth’s algorithm in terms of time delay and area occupied on the Xilinx Virtex 4vlx15sf363-12.

Implementation of a Moving Target Tracking Algorithm Using Eye-RIS Vision System on a Mobile Robot

A moving target tracking algorithm is proposed here and implemented on the Anafocus Eye-RIS vision system, which is a compact and modular platform to develop real time image processing applications. The algorithm combines moving-object detection with feature extraction in order to identify the specific target in the environment. The algorithm was tested in a mobile robotics experiment in which a robot, with the Eye-RIS mounted on it, pursued another one representing the moving target, demonstrating its performance and capabilities.

High Speed, Low complexity, Folded, Polymorphic Wavelet Architecture using Reconfigurable Hardware

The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time. I. INTRODUCTION The Discrete Wavelet Transform is used for image compression in many signal processing applications. DWT can be implemented using filter bank structures. Polymorphic DWT architecture enables the dynamic control of allocated resources to get high performance output. Polymorphism is the ability of the architecture to adapt its hardware usage to meet the desired dynamic requirements. The resultant hardware has high throughput and high image reconstruction quality, and low power consumption. This is mainly used in real time image and multimedia processing application such as video surveillance and telemedicine. Most implementations approximate the irrational coefficients to rational values, leading to image reconstruction quality tradeoffs. To overcome this Lagrange Half Band Filter [2] which can be used for the computation of rational coefficients. This method of calculation of rational filter coefficients are more accurate. Biorthogonal filters are used for implementing polymorphic DWT. In biorthogonal filter bank all the filters are finite-impulse response (FIR) filters. Biorthogonal wavelets have symmetric filter coefficients and they have orthogonality property. Symmetric filters have linear phase property which

Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform

Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an m xm edge map is serially read for processing, resulting in a total computation time of at least m(2) cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k x k grid to reduce the total computation time by a factor of k(2). We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 x 8 grid shows a 1000 x speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.

Globally Convergent Algorithms for Estimating Generalized Gamma Distributions in Fast Signal and Image Processing

Many applications in real-time signal, image, and video processing require automatic algorithms for rapid characterizations of signals and images through fast estimation of their underlying statistical distributions. We present fast and globally convergent algorithms for estimating the three-parameter generalized gamma distribution (G Gamma D). The proposed method is based on novel scale-independent shape estimation (SISE) equations. We show that the SISE equations have a unique global root in their semi-infinite domains and the probability that the sample SISE equations have a unique global root tends to one. The consistency of the global root, its scale, and index shape estimators is obtained. Furthermore, we establish that, with probability tending to one, Newton-Raphson (NR) algorithms for solving the sample SISE equations converge globally to the unique root from any initial value in its given domain. In contrast to existing methods, another remarkable novelty is that the sample SISE equations are completely independent of gamma and polygamma functions and involve only elementary mathematical operations, making the algorithms well suited for real-time both hardware and software implementations. The SISE estimators also allow the maximum likelihood (ML) ratio procedure to be carried out for testing the generalized Gaussian distribution (GGD) versus the G Gamma D. Finally, the fast global convergence and accuracy of our algorithms for finite samples are demonstrated by both simulation studies and real image analysis.

CMOS realization of two-dimensional mixed analog–digital Hamming distance discriminator circuits for real-time imaging applications

The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies on the charge-based processing of sum-of-products terms, complemented with digital post-processing. The synthesis of complex functions such as winner-(loser)-take-all, k-winner-(loser)-take-all, rank ordering are demonstrated with a minimal hardware overhead. Different operation modes and corresponding hardware configurations are presented. The VLSI realization of the core two-dimensional Hamming distance discriminator, and the chip measurements are discussed. As such, the presented Hamming discriminator is uniquely suitable for real-time image processing and alignment applications.

On VLSI design of rank-order filtering using DCRAM architecture

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μ m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7 μ m 2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply.

Multiple modular very long instruction word processors based on field programmable gate arrays

Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shorten the development cycle and to use the totality of the powerful FPGA resources in order to increase real-time performance. Some common algorithms of image processing and a face tracking in video sequences application were created and validated on an FPGA VirtexII-2000 multimedia board using the development cycle proposed. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with system-level software. This makes our approach suitable for developing co-design environments. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. In this paper, the target VLIW processor is the DSP TMS320C6x. Nonetheless, our design cycle can be generalized to other DSP processors.

Employing pipelined thinning architecture for real-time fingerprint verifier

Thinning is a very important operation in the pre-processing stage of fingerprint recognition. With the availability of fast thinning hardware, real-time image processing applications can be achieved. The authors introduce a detailed hardware architecture design of a thinning processor used in an embedded fingerprint recognition system. The proposed thinning algorithm has a parallel-pipelining structure suited to hardware realisation, which is implemented and verified using FPGA. Equipped with a modification unit array, a designated operating schedule, and an address generator based on systolic counter, this thinning processor is able to perform a thinning operation within 0.07 s at 40 MHz for a 512 � 512 picture, which is at least 40 times faster than software execution. Consequently, the proposed thinning processor was successfully integrated into a real-time fingerprint recognition system.

GPU를 이용한 실시간 이미지 프로세싱 시스템

When a real-time image processing application is implemented with a general-purpose computer, CPU (Central Processing Unit) is usually heavily loaded and in many cases that CPU alone cannot meet the real-time requirement at all. Most modern computers are equipped with powerful Graphics Processing Units (GPUs) to accelerate graphics operations. There is a trend that the power of GPU outgrows that of CPU. If we take advantage of the powerful GPU for more general operations other than pure graphics operations, the processing time can be reduced. In this study, we will present techniques that apply GPU to general operations such as image processing procedures. Our experiment results show that significant speed-up can be achieved by using GPU.