Performance Evaluation of Squaring Operation by Vedic Mathematics

Abstract

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with a small computational time (delay). As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time; therefore, it becomes imperative to concentrate on improving the speed with which we square the numbers. The squaring operation also forms the backbone in cryptography. In this paper, we propose a technique for implementing squaring operation using Vedic methods in VHDL and evaluate the performance. The results are compared with the conventional Booth’s algorithm in terms of time delay and area occupied on the Xilinx Virtex 4vlx15sf363-12.