Abstract
An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of two hundred and fifty-six taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines and implemented special processing of frames borders. Defect tolerance e.g. reconfiguration is implemented in order to enhance yield and reliability especially for future large area implementations. >
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