Readout Chip Research Articles

Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

Web-based DAQ systems: connecting the user and electronics front-ends

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Development and characterization of high-resolution neutron pixel detectors based on Timepix read-out chips

Using a suitable isotope such as 6Li and 10B semiconductor hybrid pixel detectors can be successfully adapted for position sensitive detection of thermal and cold neutrons via conversion into energetic light ions. The adapted devices then typically provides spatial resolution at the level comparable to the pixel pitch (55 μm) and sensitive area of about few cm2. In this contribution, we describe further progress in neutron imaging performance based on the development of a large-area hybrid pixel detector providing practically continuous neutron sensitive area of 71 × 57 mm2. The measurements characterising the detector performance at the cold neutron imaging instrument ICON at PSI and high-flux imaging beam-line Neutrograph at ILL are presented. At both facilities, high-resolution high-contrast neutron radiography with the newly developed detector has been successfully applied for objects which imaging were previously difficult with hybrid pixel technology (such as various composite materials, objects of cultural heritage etc.). Further, a significant improvement in the spatial resolution of neutron radiography with hybrid semiconductor pixel detector based on the fast read-out Timepix-based detector is presented. The system is equipped with a thin planar 6LiF convertor operated effectively in the event-by-event mode enabling position sensitive detection with spatial resolution better than 10 μm.

IPadPix—A novel educational tool to visualise radioactivity measured by a hybrid pixel detector

With the ability to attribute signatures of ionising radiation to certain particle types, pixel detectors offer a unique advantage over the traditional use of Geiger-Müller tubes also in educational settings. We demonstrate in this work how a Timepix readout chip combined with a standard 300μm pixelated silicon sensor can be used to visualise radioactivity in real-time and by means of augmented reality. The chip family is the result of technology transfer from High Energy Physics at CERN and facilitated by the Medipix Collaboration. This article summarises the development of a prototype based on an iPad mini and open source software detailed in ref. [1]. Appropriate experimental activities that explore natural radioactivity and everyday objects are given to demonstrate the use of this new tool in educational settings.

3D silicon pixel detectors for the High-Luminosity LHC

3D silicon pixel detectors have been investigated as radiation-hard candidates for the innermost layers of the HL-LHC upgrade of the ATLAS pixel detector. 3D detectors are already in use today in the ATLAS IBL and AFP experiments. These are based on 50 × 250 μm2 large pixels connected to the FE-I4 readout chip. Detectors of this generation were irradiated to HL-LHC fluences and demonstrated excellent radiation hardness with operational voltages as low as 180 V and power dissipation of 12–15 mW/cm2 at a fluence of about 1016 neq/cm2, measured at -25°C. Moreover, to cope with the higher occupancies expected at the HL-LHC, a first run of a new generation of 3D detectors designed for the HL-LHC was produced at CNM with small pixel sizes of 50 × 50 and 25 × 100 μm2, matched to the FE-I4 chip. They demonstrated a good performance in the laboratory and in beam tests with hit efficiencies of about 97% at already 1–2 V before irradiation.

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

A Wireless Body Sound Sensor with a Dedicated Compact Chipset

A compact wearable smart sensor for the application of wireless body sound monitoring is presented. It supports several kinds of body sound monitoring and has been measured with heart sound as an example. With the sensor, a wireless body sound monitoring system can be realized, which enables us to "build a hospital in our pocket". In order to achieve a small form factor, a dedicated highly integrated chipset has been designed for the wearable sensor. The chipset consists of a sensor readout chip for data acquisition and a 400 MHz band transceiver chip for wireless communication. It has been fabricated in CMOS technologies and can provide all the necessary sensor functions with a commercial EEPROM chip. Excluding the matching network, only eight off-chip components are required to fabricate the hardware system of the sensor, which helps to significantly improve integrated level.

High-resolution, high-linearity temperature sensor using surface acoustic wave device based on LiNbO3/SiO2/Si substrate

A high-resolution and high-linearity surface acoustic wave (SAW) temperature sensor, consisting of a SAW resonator device fabricated on novel X-cut LiNbO3/SiO2/Si piezoelectric substrate and a resonance frequency readout chip using standard 180 nm CMOS technology, is presented for the first time. High temperature performance substrate LiNbO3/SiO2/Si is prepared mainly by ion implantation and wafer bonding at first. RF SAW device with resonance frequency near 900 MHz is designed and fabricated on the substrate. Traditional probe method using network analyzer and the readout chip method are both implemented to characterize the fabricated SAW device. Further measurement of temperature using resonance frequency shift of SAW device demonstrates the feasibility of the combined system as a portable SAW temperature sensor. The obtained frequency-temperature relation of the fabricated device is almost linear. The frequency resolution of the readout chip is 733 Hz and the corresponding temperature accuracy is 0.016 ° C. Resolution of the sensor in this work is superior to most of the commercial temperature measurement sensors. Theory analysis and finite element simulation are also presented to prove the mechanism and validity of using SAW device for temperature detection applications. We conclude that the high-linearity frequency-temperature relation is achieved by the offset between high-order coefficients of LiNbO3 and SiO2 with opposite signs. This work offers the possibility of temperature measuring in ultra-high precision sensing and control applications.

HEPS-BPIX, a single photon counting pixel detector with a high frame rate for the HEPS project

China's next generation light source, named the High Energy Photon Source (HEPS), is currently under construction. HEPS-BPIX (HEPS-Beijing PIXel) is a dedicated pixel readout chip that operates in single photon counting mode for X-ray applications in HEPS. Designed using CMOS 0.13µm technology, the chip contains a matrix of 104×72 pixels. Each pixel measures 150µm×150µm and has a counting depth of 20bits. A bump-bonded prototyping detector module with a 300-µm thick silicon sensor was tested in the beamline of Beijing Synchrotron Radiation Facility. A fast stream of X-ray images was demonstrated, and a frame rate of 1.2kHz was proven, with a negligible dead time. The test results showed an equivalent noise charge of 115e−rms after bump bonding and a threshold dispersion of 55e−rms after calibration.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

Dependence of SQUID Intrinsic Flux Noise on Stewart–McCumber Parameter <inline-formula> <tex-math notation="LaTeX">$\beta_{c}$</tex-math> </inline-formula> of Josephson Junction

It is known that three superconducting quantum interference device (SQUID) parameters, namely, the intrinsic flux noise δΦ s , the flux-to-voltage transfer coefficient ∂V/∂Φ, and the dynamic resistance R d , increase with increasing the Stewart- McCumber parameter β c of Josephson junction. It is very difficult to obtain the low values of δΦ s for a strongly damped SQUID due to its small ∂V/∂Φ. In this paper, we employ a two-stage scheme (TSS) to measure δΦ s directly. Here, we use single chip readout electronics and a weakly damped SQUID with a β c of flux noise of the readout-SQUID system is about 4.8 μΦ 0 /√Hz 1.2, both acting as a readout-SQUID system (a preamplifier). The with a corner frequency of about 10 Hz. The front-end SQUID is coupled to the readout SQUID via the input coil with a mutual inductance of M i . In our experiment, the flux gain for a readout SQUID, i.e., G Φ = M i × (∂I/∂Φ) front-end is adjusted to be 20. Using the TSS, we measured δΦ s with different β c changing from 0.3 to 13.5 and found δΦ s increasing from 1.0 to 5.0 μΦ 0 /√Hz. We also discussed the relations between L s , β c , and δΦ s quantitatively. Finally, we proposed designing a suitable β c to match the preamplifier in a direct readout scheme to simplify a SQUID measurement system.

Characterisation of strip silicon detectors for the ATLAS Phase-II Upgrade with a micro-focused X-ray beam

The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 6·1034 cm−2s−1. A consequence of this increased luminosity is the expected radiation damage at 3000 fb−1 after ten years of operation, requiring the tracking detectors to withstand fluences to over 1·1016 1 MeV neq/cm2. In order to cope with the consequent increased readout rates, a complete re-design of the current ATLAS Inner Detector (ID) is being developed as the Inner Tracker (ITk).Two proposed detectors for the ATLAS strip tracker region of the ITk were characterized at the Diamond Light Source with a 3 μm FWHM 15 keV micro focused X-ray beam. The devices under test were a 320 μm thick silicon stereo (Barrel) ATLAS12 strip mini sensor wire bonded to a 130 nm CMOS binary readout chip (ABC130) and a 320 μm thick full size radial (end-cap) strip sensor - utilizing bi-metal readout layers - wire bonded to 250 nm CMOS binary readout chips (ABCN-25).A resolution better than the inter strip pitch of the 74.5 μm strips was achieved for both detectors. The effect of the p-stop diffusion layers between strips was investigated in detail for the wire bond pad regions.Inter strip charge collection measurements indicate that the effective width of the strip on the silicon sensors is determined by p-stop regions between the strips rather than the strip pitch.

The Phase-1 upgrade of the CMS pixel detector

The CMS experiment features a pixel detector with three barrel layers and two discs per side, corresponding to an active silicon area of 1m2. The detector delivered high-quality data during LHC Run 1. However, the CMS pixel detector was designed for the nominal instantaneous LHC luminosity of 1·1034cm−2s−1. It is expected that the instantaneous luminosity will increase and reach twice the design value before Long Shutdown 3, scheduled for 2023. Under such conditions, the present readout chip would suffer from data loss due to buffer overflow, leading to significant inefficiencies of up to 16%. The CMS collaboration is presently constructing a new pixel detector to replace the present device during the winter shutdown 2016/2017. The design of this new detector will be outlined, the construction status summarized and the performance described.

Thin hybrid pixel assembly fabrication development with backside compensation layer

The ATLAS and CMS experiments will both replace their entire tracking systems for operation at the HL-LHC in 2026. This will include a significantly larger pixel systems, for example, for ATLAS approximately 15m2. To keep the tracker material budget low it is crucial to minimize the mass of the pixel modules via thinning both the sensor and readout chip to about 150μm each. The bump yield of thin module assemblies using solder based bump bonding can be problematic due to wafer bowing during solder reflow at high temperature. A new bump-bonding process using backside compensation on the readout chip to address the issue of low yield will be presented. The objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the backside of the wafer. A SiN and Al:Si stack has been chosen for the backside layer. The bow reducing effect of applying a backside compensation layer will be demonstrated using the FE-I4 wafer. The world's first results from assemblies produced from readout wafers thinned to 100μm with a stress compensation layer are presented with bond yields close to 100% measured using the FE-I4 readout chip.

Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

The CMS Binary Chip (CBC) is a prototype version of the front-end read-out ASIC to be used in the silicon strip modules of the CMS outer tracking detector during the high luminosity phase of the LHC. The CBC is produced in 130nm CMOS technology and bump-bonded to the hybrid of a double layer silicon strip module, the so-called 2S-pT module. It has 254 input channels and is designed to provide on-board trigger information to the first level trigger system of CMS, with the capability of cluster-width discrimination and high-pT track identification. In November 2013 the first 2S-pT module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2 to 4GeV. In this paper the test setup and the results are presented.

A Touch Prediction and Window Sensing Strategy for Low-Power and Low-Cost Capacitive Multitouch Screen Systems

A new multitouch sensing strategy, named the Touch Prediction and Window Sensing (TPWS), is proposed and realized in this paper for projected capacitive touch screens. The detection procedures of TPWS are divided into two stages: a pre-sensing stage for predicting the possible touched regions, and a window sensing stage for obtaining the accurate touched positions. Since the measurements of the untouched sensing cells are reduced significantly, the TPWS strategy needs lower efforts on signal readout and data processing than the traditional strategies. A prototype system was designed and realized, which consists of three identical 48-channel readout chips, a 15-in capacitive touch screen, and a commercial host processor. The readout chip is specially designed for the TPWS strategy using $\hbox{0.13}~\mu\hbox{m}$ 1.8 V/5 V CMOS process. The measurement results show that, the total power consumption of the system is only about 65 mW with a power supply of 5 V, and the reporting rate of the system achieves 500 Hz for no touches and 83 Hz for ten touches. The area of the readout chip is only 0.087 $ ~\hbox{mm}^{2}$ per sensing channel. The proposed TPWS strategy can be used to realize low-power and low-cost multitouch screen system, and it is especially efficient for large-sized screen.

Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100μm2). These dimensions are foreseen for the new ATLAS read-out chip in 65nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50μm2 pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

Overview of the Micro Vertex Detector for the [formula omitted]ANDA experiment

The P¯ANDA experiment is devoted to study interactions between cooled antiproton beams and a fixed target (the interaction rate is of about 107 events/s), hydrogen or heavier nuclei. The innermost tracker of P¯ANDA is the Micro Vertex Detector (MVD), specially designed to ensure the secondary vertex resolution for the discrimination of short-lived charmonium states. Hybrid epitaxial silicon pixels and double-sided silicon microstrips will equip four barrels, arranged around the interaction point, and six forward disks. The experiment features a triggerless architecture with a master clock of 160MHz, therefore the MVD has to run with a continuous data transmission where the hits need precise timestamps. The energy loss of the particles in the sensor will be measured as well. The challenging request of a triggerless readout suggested to develop custom readout chips for both pixel (ToPix) and microstrip (PASTA) devices. To validate components and the triggerless readout architecture, prototypes have been built and tested. After an overview of the MVD, the technological aspects and performances of some prototypes will be reported.

Study and optimization of the spatial resolution for detectors with binary readout

Using simulations and analytical approaches, we have studied single hit resolutions obtained with a binary readout, which is often proposed for high granularity detectors to reduce the generated data volume. Our simulations considering several parameters (e.g. strip pitch) show that the detector geometry and an electronics parameter of the binary readout chips could be optimized for binary readout to offer an equivalent spatial resolution to the one with an analog readout. To understand the behavior as a function of simulation parameters, we developed analytical models that reproduce simulation results with a few parameters. The models can be used to optimize detector designs and operation conditions with regard to the spatial resolution.

The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system.This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.