Abstract
This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.
Highlights
Analog Very Front End electronics and IP-blocksFour different analog very front-ends (VFE) (CSA, discriminator, signal processing) have been developed [6, 7]
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Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits
Summary
Four different analog very front-ends (VFE) (CSA, discriminator, signal processing) have been developed [6, 7]. All designs are: compact with area below 35 × 35 mum; low-noise with ENC below 100 electrons for a value of input capacitance of 50 fF typical for a silicon sensor; low power; fast, allowing correct time-stamp with 25 ns accuracy. Three designs use 4-bit Time Over Threshold technique (ToT) for signal digitisation, while one using a flash-ADC per pixel is limited to 3-bit in order to limit power consumption. All VFE are capable to provide to each pixel 10 nA leakage current to a silicon sensor. Dead Time loss Trigger rate / latency Low In-time Threshold Total Ionizing Dose (TID) Hit charge resolution Total power per pixel
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