Thin hybrid pixel assembly fabrication development with backside compensation layer

Abstract

The ATLAS and CMS experiments will both replace their entire tracking systems for operation at the HL-LHC in 2026. This will include a significantly larger pixel systems, for example, for ATLAS approximately 15m2. To keep the tracker material budget low it is crucial to minimize the mass of the pixel modules via thinning both the sensor and readout chip to about 150μm each. The bump yield of thin module assemblies using solder based bump bonding can be problematic due to wafer bowing during solder reflow at high temperature. A new bump-bonding process using backside compensation on the readout chip to address the issue of low yield will be presented. The objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the backside of the wafer. A SiN and Al:Si stack has been chosen for the backside layer. The bow reducing effect of applying a backside compensation layer will be demonstrated using the FE-I4 wafer. The world's first results from assemblies produced from readout wafers thinned to 100μm with a stress compensation layer are presented with bond yields close to 100% measured using the FE-I4 readout chip.