Read Operation Research Articles

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes. Process, voltage, and temperature fluctuation significantly influence several performance characteristics, making it a crucial concern in nanometer SRAM design. This study presents two novel SRAM designs that effectively decrease power consumption during read operations without compromising performance or stability. A 14T SRAM has been built with an architecture that enables single-ended write and differential read operations. In addition, a 13T SRAM has been developed using an architecture that incorporates a differential write and single-ended read operation with the assistance of a write-read circuit. The two suggested SRAM cells have been fabricated using the CMOS 45 nm technology. The provided study examines the impact of modifications in process parameters on several design metrics, including the proposed cell's read-write power and current. These metrics are then compared with those of a previously suggested SRAM cell. The read power consumption of the 14T SRAM cell is reduced by 20 %, 60.63 %, 34.73 % 53.68 %, when compared to CS6T, SS8T, SS10T, and SEW10T. For the proposed 13T SRAM, the read power consumption is reduced by 147.40 %, 230.43 %, 178.2 % 217.39 %, 30.4 % when compared to CS6T, SS8T,SS10T, SEW10T, SER11T. Also the proposed SRAM II has 106.52 % lower read power when compared with proposed 14T SRAM. Also the write power of the proposed 13T SRAM is at lower side when compared to others but at the sametime write power of proposed 14T suffers from higher power consumption. Therefore the proposed 13T SRAM has been considered for the further evaluation. The RSNM and WSNM show atleast 5 % improvement when compared to existing architectures.

A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories

In this paper, a novel read scheme using gate-induced drain leakage (GIDL) current is proposed to suppress read disturbance in 3-D NAND flash memories. The proposed read scheme is demonstrated through the technology computer-aided design (TCAD) simulation. In the selected string, GIDL current is not generated due to the low potential difference. On the other hand, in the unselected string, holes are accumulated under the selected cell and potential of the selected cell is enhanced due to the GIDL current before the read operation. The potential differences between the selected and adjacent cells are decreased and maximum electric field (Em) is decreased. Therefore, soft programming in the selected cell during the read operation is decreased and hot carrier injection (HCI) between selected and adjacent cells is reduced completely. The proposed read scheme can be applied to high stacked WL layers over 200 layers.

Hybrid Time/Phase Domain Synchronous Electromagnetic Encoders for Near-Field Chipless-RFID and Motion Control Applications

Synchronous electromagnetic encoder systems exploiting phase encoding to boost up the number of bits per encoder position are reported in this article. The reader is a one-port structure consisting of a transmission line terminated with a matched load and fed by a harmonic (single tone) signal. The encoders, or tags, are implemented by means of a single chain of strip resonators (inclusions) printed or etched on a dielectric substrate and oriented transversally to the chain axis. Phase encoding is achieved through the transverse position of the strips in the chain. Thus, in a reading operation, the encoder is displaced at a very short distance over the reader, in the direction orthogonal to the line axis. By this means, the resonant strips of the encoder cross the line in perfect alignment with it, significantly perturbing the reflection (and transmission) coefficient. By tuning the frequency of the feeding signal to the resonance frequency of the strips, total reflection is (roughly) expected each time a resonant strip is on top of the line. Moreover, under perfect alignment between the line and a resonant strip, the phase of the reflection coefficient depends on the distance between the inclusion (resonant strip) and the input port. Therefore, the identification (ID) associated with that inclusion can be retrieved by measuring the phase of the reflection coefficient. The number of states (and hence bits) per encoder position in the chain depends on the number of different transverse positions of the inclusions that can be resolved (16 in the prototype reported in this article). The achieved density of bits per unit length is DPL <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 5.71 bit/cm and per unit surface is DPS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 0.57 bit/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Nevertheless, the main relevant advantage of the proposed phase-modulated (PM) system is the fact that a single harmonic signal suffices for tag reading, contrary to other synchronous electromagnetic encoder systems based on frequency encoding, where multiple feeding harmonic signals are needed.

OptiQL: Robust Optimistic Locking for Memory-Optimized Indexes

Modern memory-optimized indexes often use optimistic locks for concurrent accesses. Read operations can proceed optimistically without taking the lock, greatly improving performance on multicore CPUs. But this is at the cost of robustness against contention where many threads contend on a small set of locks, causing excessive cacheline invalidation, interconnect traffic and eventually performance collapse. Yet existing solutions often sacrifice desired properties such as compact 8-byte lock size and fairness among lock requesters. This paper presents optimistic queuing lock (OptiQL), a new optimistic lock for database indexing to solve this problem. OptiQL extends the classic MCS lock---a fair, compact and robust mutual exclusion lock---with optimistic read capabilities for index workloads to achieve both robustness and high performance while maintaining various desirable properties. Evaluation using memory-optimized B+-trees on a 40-core, dual-socket server shows that OptiQL matches existing optimistic locks for read operations, while avoiding performance collapse under high contention.

Applying self-powered sensor and support vector machine in load energy consumption modeling and prediction of relational database

This study explores the analysis and modeling of energy consumption in the context of database workloads, aiming to develop an eco-friendly database management system (DBMS). It leverages vibration energy harvesting systems with self-sustaining wireless vibration sensors (WVSs) in combination with the least square support vector machine algorithm to establish an energy consumption model (ECM) for relational database workloads. Through experiments, the performance of self-sustaining WVS in providing power is validated, and the accuracy of the proposed ECM during the execution of Structured Query Language (SQL) statements is evaluated. The findings demonstrate that this approach can reliably predict the energy consumption of database workloads, with a maximum prediction error rate of 10% during SQL statement execution. Furthermore, the ECM developed for relational databases closely approximates actual energy consumption for query operations, with errors ranging from 1 to 4%. In most cases, the predictions are conservative, falling below the actual values. This finding underscores the high predictive accuracy of the ECM in anticipating relational database workloads and their associated energy consumption. Additionally, this paper delves into prediction accuracy under different types of operations and reveals that ECM excels in single-block read operations, outperforming multi-block read operations. ECM exhibits substantial accuracy in predicting energy consumption for SQL statements in sequential and random read modes, especially in specialized database management system environments, where the error rate for the sequential read model is lower. In comparison to alternative models, the proposed ECM offers superior precision. Furthermore, a noticeable correlation between model error and the volume of data processed by SQL statements is observed. In summary, the relational database ECM introduced in this paper provides accurate predictions of workload and database energy consumption, offering a theoretical foundation and practical guidance for the development of eco-friendly DBMS.

Performance analysis of LogisticChain: A blockchain platform for maritime logistics

The application of blockchain and smart contracts has been widely acknowledged as essential in digitised logistics, offering improved traceability, transparency, and efficiency. However, concerns regarding performance and implementation limitations persist. To demonstrate the challenges regarding the performance and efficiency of blockchain in logistics use cases, this study presents a proof-of-concept model by leveraging the Hyperledger Fabric blockchain network to emulate the shipping logistics process and illustrate the automated and self-executing nature of smart contracts and transactions among various logistics participants by implementing RAFT consensus mechanism. Utilizing Hyperledger Caliper, this study evaluates the performance by systematically adjusting parameters including the number of clients, the number of concurrent transactions, and transaction rates per second. Then nuanced variations in latency, send rate, and throughput are examined. Preliminary findings indicate significant performance impacts related to client numbers and transaction rates per second. When exceeding the processing capacity, the average latency of transactions experiences an exponential increase due to limited resources. Furthermore, different types of operations are compared, with Read operations exhibiting the lowest latency and Update operations displaying the highest latency due to the complex computations and validations involved. Lastly, the latency measures of the LogisticChain network between fixed-rate and linear-rate controllers are compared, highlighting lower latency with fixed-rate controllers. This research contributes to the advancement of knowledge in this field by developing open-source codes specifically tailored for maritime logistics use cases.

Design and analysis of FIFO system based on basic circuit functions

Due to the insufficient data acquisition rate and high power consumption of sensors, this article focuses on addressing the issue of clock cycle interaction error resulting from the excessive amount of data on integrated circuit chips. Specifically, a FIFO design is proposed to achieve the transmission and transformation of data under different clock cycles. The technical challenges associated with creating an asynchronous FIFO, reducing the probability of encountering semi-stable states, and achieving delay control are analyzed in this paper. To tackle the semi-stable error, a Gray code converter and two-stage synchronizer are employed. The designed FIFO also leverages the difference and phase difference of read and write pointers to achieve high-accuracy delay control. The experiments demonstrate that the designed FIFO can successfully facilitate correct writing and reading operations. Through Modelsim simulation tests, the waveform is more precise than before, and the operation of the designed FIFO is realized.

A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application

The decreasing operational voltage and scaled technology node for memory designing has widened the gap between two crucial parameters for an SRAM – delay and power. As the demand for internet of things is increasing, the need for round the clock connectivity is increasing. This mandates designing a cell with a capability to switch between low power and high speed operation. Thus, this paper presents the design of dual mode operational 7T cell that can switch between single port and dual port configuration. The proposed reconfigurable cell can operate as single port or dual port cell single ended 7T cell. The reconfigurability in the cell is realized using control signals. The noise stability of the bit cell is obtained to be 333, 333, and 470 mV for read, hold, and write modes, respectively. The robustness of the cell against temperature variation, process variation and voltage variation is also analyzed. The performance variation in each parameter will not have a dramatic impact as it is within manageable limit. Its write time is 0.14 ns, while 5 ps are required for a successful read operation. The dual port configuration of the cell supports pipelining and thus operates faster than its single port configuration.

Non-Invasive Mapping of the Neuronal Networks of Language.

This review consists of three main sections. In the first, the Introduction, the main theories of the neuronal mediation of linguistic operations, derived mostly from studies of the effects of focal lesions on linguistic performance, are summarized. These models furnish the conceptual framework on which the design of subsequent functional neuroimaging investigations is based. In the second section, the methods of functional neuroimaging, especially those of functional Magnetic Resonance Imaging (fMRI) and of Magnetoencephalography (MEG), are detailed along with the specific activation tasks employed in presurgical functional mapping. The reliability of these non-invasive methods and their validity, judged against the results of the invasive methods, namely, the "Wada" procedure and Cortical Stimulation Mapping (CSM), is assessed and their use in presurgical mapping is justified. In the third and final section, the applications of fMRI and MEG in basic research are surveyed in the following six sub-sections, each dealing with the assessment of the neuronal networks for (1) the acoustic and phonological, (2) for semantic, (3) for syntactic, (4) for prosodic operations, (5) for sign language and (6) for the operations of reading and the mechanisms of dyslexia.

Tampering with the flash memory of microcontrollers: permanent fault injection via laser illumination during read operations

Tampering with the flash memory of microcontrollers: permanent fault injection via laser illumination during read operations

High‐Resolution Single Photon Level Storage of Telecom Light Based on Thin Film Lithium Niobate Photonics

AbstractThis study presents an experimental analysis of high‐resolution single photon buffers based on low‐loss thin film lithium niobate (TFLN) photonic devices operating at room temperature. While dynamically controlling writing and reading operations within picosecond timescales poses a challenge, the devices are capable of resolving 102.8 ± 4.6 ps time step with ‐0.89 dB loss per round‐trip and 197.7 ± 6.6 ps time steps with ‐1.29 dB loss per round‐trip, respectively. These results imply that the devices are at the cutting edge of on‐chip technology, performing in the current state of the art at the single photon level. Both of the single photon buffers do not introduce any detrimental effects and provide a high signal‐to‐noise ratio (SNR). The room‐temperature, low‐loss, and voltage‐controlled TFLN buffers combine scalable architecture with relatively high buffering capacity in the sub‐nanosecond regime and are expected to unlock many novel photonics applications such as temporally multiplexed single photon sources.

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements

With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interlocked storage cell (DICE) element, which exhibit severe limitations: charge sharing during the read operation at a system level and large power consumption. Overcoming these limitations, this brief proposes a DNU-resilient latch based on a novel latch element. The proposed latch fully exploits upset polarity awareness, achieving the maximum number of single-event upset (SEU)-insensitive nodes. We develop a novel double modular redundancy architecture for the DNU-resilient latch design with one SEU-immune module. Based on simulation results, the proposed latch achieves up to 27.6X average power-delay-area-product (PDAP) improvement over state-of-the-art DNU-resilient latches.

Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability

Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.

Expanded Noise Margin 10T SRAM Cell using Finfet Device

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential.

Data Transaction using AHB Protocol

Data Transaction using AHB Protocol

An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV

An approach to the implementation of a neural network for real-time cryptographic data protection with symmetric keys oriented on embedded systems is presented. This approach is valuable, especially for onboard communication systems in unmanned aerial vehicles (UAV), because of its suitability for hardware implementation. In this study, we evaluate the possibility of building such a system in hardware implementation at FPGA. Onboard implementation-oriented information technology of real-time neuro-like cryptographic data protection with symmetric keys (masking codes, neural network architecture, and matrix of weighting coefficients) has been developed. Due to the pre-calculation of matrices of weighting coefficients and tables of macro-partial products and the use of tabular-algorithmic implementation of neuro-like elements and dynamic change of keys, it provides increased cryptographic stability and hardware–software implementation on FPGA. The table-algorithmic method of calculating the scalar product has been improved. By bringing the weighting coefficients to the greatest common order, pre-computing the tables of macro-partial products, and using operations of memory read, fixed-point addition, and shift operations instead of floating-point multiplication and addition operations, it provides a reduction in hardware costs for its implementation and calculation time as well. Using a processor core supplemented with specialized hardware modules for calculating the scalar product, a system of neural network cryptographic data protection in real-time has been developed, which, due to the combination of universal and specialized approaches, software, and hardware, ensures the effective implementation of neuro-like algorithms for cryptographic encryption and decryption of data in real-time. The specialized hardware for neural network cryptographic data encryption was developed using VHDL for equipment programming in the Quartus II development environment ver. 13.1 and the appropriate libraries and implemented on the basis of the FPGA EP3C16F484C6 Cyclone III family, and it requires 3053 logic elements and 745 registers. The execution time of exclusively software realization of NN cryptographic data encryption procedure using a NanoPi Duo microcomputer based on the Allwinner Cortex-A7 H2+ SoC was about 20 ms. The hardware–software implementation of the encryption, taking into account the pre-calculations and settings, requires about 1 msec, including hardware encryption on the FPGA of four 2-bit inputs, which is performed in 160 nanoseconds.

Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller

Researchers in the field of device research are always searching for a device that meets certain criteria, such as having low leakage and a low threshold voltage, without sacrificing performance. This pursuit has led to the development of numerous gate architectures. As a result of the enormous size of the static random-access memory (SRAM), its yield and leakage power consumption account for the majority of the chip’s total yield and leakage power consumption respectively. However, as CMOS technology continues to grow in the sub-65 nanometer domain to lower the cost of transistors and the dynamic power, it presents a number of issues on the design of SRAM. In this paper, a 6T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 6T cell which uses high and low VTH transistors to improve the read and write stability. Also, the changes of cell parameters when the temperature rises from 40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell are studied at two supply voltages of 400 mV and 500 mV.

Capacitive Memory Window With Non-Destructive Read in Ferroelectric Capacitors

Energy-efficient memory elements having a non-volatile memory window (MW) with a non-destructive read operation are highly desirable for both random access memory and compute-in-memory applications. In this work, we demonstrate a record high non-volatile capacitive MW and non-destructive read in hafnium zirconate-based metal-ferroelectric-metal capacitors (FeCAPs). Firstly, we show that a non-zero capacitive MW at zero read voltage can be realized by engineering an asymmetry between the top and bottom ferroelectric-metal interfaces and demonstrate a record high MW of ~4.71×ϵ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> at 0 V. Secondly, we show that the capacitive MW can be further improved by optimizing a non-zero read voltage. This allows to achieve a record high MW of ~7.5×ϵ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> for the asymmetric FeCAP, and even opens up a MW as high as ~8.0×ϵ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> for the symmetric FeCAP. Finally, we demonstrate that the MW can be reliably read non-destructively as long as the read voltage is carefully selected to avoid partial or full polarization switching during the read operation.

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

The Ferroelectric Field-Effect Transistor (FeFET) is an emerging technology enabling novel data-centric architectures that go far beyond von Neumann principles. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as a novel structure that offers for the first time disturb-free read operation along with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 10× larger memory window (MW) compared to conventional FeFETs. However, all the before-mentioned variations are amplified in such a new structure. This work analyses the impact of temperature variation for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels, and compared to conventional FeFET. Through our cross-layer framework, we demonstrate the severe impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even Hyperdimensional Computing is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.