Design and analysis of FIFO system based on basic circuit functions

Abstract

Due to the insufficient data acquisition rate and high power consumption of sensors, this article focuses on addressing the issue of clock cycle interaction error resulting from the excessive amount of data on integrated circuit chips. Specifically, a FIFO design is proposed to achieve the transmission and transformation of data under different clock cycles. The technical challenges associated with creating an asynchronous FIFO, reducing the probability of encountering semi-stable states, and achieving delay control are analyzed in this paper. To tackle the semi-stable error, a Gray code converter and two-stage synchronizer are employed. The designed FIFO also leverages the difference and phase difference of read and write pointers to achieve high-accuracy delay control. The experiments demonstrate that the designed FIFO can successfully facilitate correct writing and reading operations. Through Modelsim simulation tests, the waveform is more precise than before, and the operation of the designed FIFO is realized.