Reactive Ion Etching Lag Research Articles

Assessing neutral transport mechanisms in aspect ratio dependent etching by means of experiments and multiscale plasma modeling

Since the onset of pattern transfer technologies for chip manufacturing, various strategies have been developed to circumvent or overcome aspect ratio dependent etching (ARDE). These methods have, however, their own limitations in terms of etch non-idealities, throughput or costs. Moreover, they have mainly been optimized for individual in-device features and die-scale patterns, while occasionally ending up with poor patterning of metrology marks, affecting the alignment and overlay in lithography. Obtaining a better understanding of the underlying mechanisms of ARDE and how to mitigate them therefore remains a relevant challenge to date, for both marks and advanced nodes. In this work, we accordingly assessed the neutral transport mechanisms in ARDE by means of experiments and multiscale modeling for SiO2 etching with CHF3/Ar and CF4/Ar plasmas. The experiments revealed a local maximum in the etch rate for an aspect ratio around unity, i.e. the simultaneous occurrence of regular and inverse reactive ion etching lag for a given etch condition. We were able to reproduce this ARDE trend in the simulations without taking into account charging effects and the polymer layer thickness, suggesting shadowing and diffuse reflection of neutrals as the primary underlying mechanisms. Subsequently, we explored four methods with the simulations to regulate ARDE, by varying the incident plasma species fluxes, the amount of polymer deposition, the ion energy and angular distribution and the initial hardmask sidewall angle, for which the latter was found to be promising in particular. Although our study focusses on feature dimensions characteristic to metrology marks and back-end-of-the-line integration, the obtained insights have a broader relevance, e.g. to the patterning of advanced nodes. Additionally, this work supports the insight that physisorption may be more important in plasma etching at room temperature than originally thought, in line with other recent studies, a topic on which we recommend further research.

A sleeve and bulk method for fabrication of photonic structures with features on multiple length scales

Traditional photonic structures such as photonic crystals utilize (a) large arrays of small features with the same size and pitch and (b) a small number of larger features such as diffraction outcouplers. In conventional nanofabrication, separate lithography and etch steps are used for small and large features in order to employ process parameters that lead to optimal pattern transfer and side-wall profiles for each feature-size category, thereby overcoming challenges associated with reactive ion etching lag. This approach cannot be scaled to more complex photonic structures such as those emerging from inverse design protocols. Those structures include features with a large range of sizes such that no distinction between small and large can be made. We develop a sleeve and bulk etch protocol that can be employed to simultaneously pattern features over a wide range of sizes while preserving the desired pattern transfer fidelity and sidewall profiles. This approach reduces the time required to develop a robust process flow, simplifies the fabrication of devices with wider ranges of feature sizes, and enables the fabrication of devices with increasingly complex structure.

Etch-free additive lithographic fabrication methods for reflective and transmissive micro-optics.

With the widespread application of micro-optics in a large range of areas, versatile high quality fabrication methods for diffractive optical elements (DOEs) have always been desired by both the research community and by industry. Traditionally, multi-level DOEs are fabricated by a repetitive combination of photolithography and reactive-ion etching (RIE). The optical phase accuracy and micro-surface quality are severely affected by various etching artifacts, e.g., RIE lag, aspect ratio dependent etching rates, and etching artifacts in the RIE steps. Here we propose an alternative way to fabricate DOEs by additively growing multi-level microstructures onto the substrate. Depth accuracy, surface roughness, uniformity and smoothness are easily controlled to high accuracy by a combination of deposition and lift-off, rather than etching. Uniform depths can be realized for both micrometer and millimeter scale features that are simultaneously present in the designs. The grown media can either be used directly as a reflective DOE, or as a master stamp for nanoimprinting refractive designs. We demonstrate the effectiveness of the fabrication methods with representative reflective and transmissive DOEs for imaging and display applications.

Reduced Etch Lag and High Aspect Ratios by Deep Reactive Ion Etching (DRIE).

Deep reactive ion etching (DRIE) with the Bosch process is one of the key procedures used to manufacture micron-sized structures for MEMS and microfluidic applications in silicon and, hence, of increasing importance for miniaturisation in biomedical research. While guaranteeing high aspect ratio structures and providing high design flexibility, the etching procedure suffers from reactive ion etching lag and often relies on complex oxide masks to enable deep etching. The reactive ion etching lag, leading to reduced etch depths for features exceeding an aspect ratio of 1:1, typically causes a height difference of above 10% for structures with aspect ratios ranging from 2.5:1 to 10:1, and, therefore, can significantly influence subsequent device functionality. In this work, we introduce an optimised two-step Bosch process that reduces the etch lag to below 1.5%. Furthermore, we demonstrate an improved three-step Bosch process, allowing the fabrication of structures with width at depths up to while maintaining their stability.

Increase of space width roughness in directed self-assembly patterning arising from shrinking stress in the remaining poly(methyl methacrylate)

The mechanism for the increase in space width roughness (SWR) after selective poly(methyl methacrylate) (PMMA) etching to polystyrene (PS) is investigated for directed self-assembly patterning. Considering the cross-sectional image obtained from field-emission scanning electron microscopy, the authors propose a physical model where the shrinking stress in the remaining PMMA with thickness variation induces PS-line collapse and this collapse increases SWR. Linear finite-element calculations show that this proposed model can explain two experimental results; namely, the SWR exhibits a peak that depends on the thickness of the remaining PMMA and the low-frequency component of SWR becomes larger after etching. To prove our model more directly, PMMA was shrunk by electron beam (EB) irradiation and the change in SWR was examined. SWR with residual PMMA increased with an increasing EB-dose amount, while SWR without residual PMMA did not show a clear increasing trend. These results clearly show the shrinking stress in the remaining PMMA with thickness variation increases SWR. To suppress the SWR increase during etching, the etching condition was also modified based on our model. Intrinsic-shrinking stress in PMMA was reduced by a carbon-oxygen mixture plasma. In addition, the thickness variation of the remaining PMMA was suppressed by the reduction of the reactive ion etching lag with a dual-time modulated (DTM) plasma. Eventually, an SWR less than the incoming value was realized by using a carbon-oxygen mixture plasma with DTM.

DREM: Infinite etch selectivity and optimized scallop size distribution with conventional photoresists in an adapted multiplexed Bosch DRIE process

The quest to sculpture materials as small and deep as possible is an ongoing topic in micro- and nanofabrication. For this, the Bosch process has been widely used to achieve anisotropic silicon microstructures with high aspect ratio. Reactive ion etching (RIE) lag is a phenomenon in which etch rate depends on the opening areas of patterns, aspect ratio of the trenches and other geometrical factors. The lag not only gives a non-uniform distribution of scallop size, but it also sets a limit for the maximum achievable aspect ratio. The latter since the mask suffers from persistent erosion. While different kinds of hard masks have been suggested to ensure a longer total etch time, here we report a correctly tuned 3-steps Bosch process – called DREM (Deposit, Remove, Etch, Multistep) – without mask erosion. The erosion-free feature is independent of the type of mask. For example, an aspect ratio of more than 50 is achieved for trenches with 1μm linewidths, while no erosion is observed for 360nm thin standard photoresists. The mechanism behind this extraordinary infinite selectivity is mainly due to the depletion of C4F8 deposition species. Furthermore, a linear ramping of the etch step duration is performed to achieve a uniform distribution of scallop sizes along the etch profile. This outperforms the usual broad scallop size distribution when no parameter ramping is performed and improves the straightness of the etch profile considerably, in addition, it allows an easier way to control periodic sidewall shaping. e.g., a sausage-chain-like feature is demonstrated with an almost perfect periodicity.

3D Insulator-based dielectrophoresis using DC-biased, AC electric fields for selective bacterial trapping.

Insulator-based dielectrophoresis (iDEP) is a well-known technique that harnesses electric fields for separating, moving, and trapping biological particle samples. Recent work has shown that utilizing DC-biased AC electric fields can enhance the performance of iDEP devices. In this study, an iDEP device with 3D varying insulating structures analyzed in combination with DC biased AC fields is presented for the first time. Using our unique reactive ion etch lag, the mold for the 3D microfluidic chip is created with a photolithographic mask. The 3D iDEP devices, whose largest dimensions are 1 cm long, 0.18 cm wide, and 90μm deep are then rapidly fabricated by curing a PDMS polymer in the glass mold. The 3D nature of the insulating microstructures allows for high trapping efficiency at potentials as low as 200 Vpp. In this work, separation of Escherichia coli from 1 μm beads and selective trapping of live Staphylococcus aureus cells from dead S. aureus cells is demonstrated. This is the first reported use of DC-biased AC fields to selectively trap bacteria in 3D iDEP microfluidic device and to efficiently separate particles where selectivity of DC iDEP is limited.

A study on reactive ion etching lag of a high aspect ratio contact hole in a magnetized inductively coupled plasma

Reactive ion etching lag (RIE lag) characteristics of a high aspect ratio contact hole in a magnetized inductively coupled plasma (M-ICP) etcher were investigated. The dependence of RIE lag on various process parameters, such as neutral gas pressure, magnetic flux density, bias power, bias frequency, and source power were investigated. It was confirmed that RIE lag could be reduced by properly adjusting these variables. Furthermore, the application of a magnetic field to the ICP etcher was helpful to increase the oxide etch rate and oxide-to-amorphous carbon layer selectivity.

Bio-inspired microstructures in collagen type I hydrogel.

This article presents a novel technique to fabricate complex type I collagen hydrogel structures, with varying depth and width defined by a single fabrication step. This technique takes advantage of reactive ion etching lag to fabricate three-dimensional (3-D) structures in silicon. Then, a polydimethylsiloxane replica was fabricated utilizing soft lithography and used as a stamp on collagen hydrogel to transfer these patterns. Endothelial cells were seeded on the hydrogel devices to measure their interaction with these more physiologically relevant cell culture surfaces. Confocal imaging was utilized to image the hydrogel devices to demonstrate the robustness of the fabrication technique, and to study the cell-extracellular matrix interaction after cell seeding. In this study, we observed that endothelial cells remodeled the sharp scallops of collagen hydrogel structures and compressed the structures with low degree of slope. Such patterning techniques will enhance the physiological relevance of existing 3-D cell culture platforms by providing a technical bridge between the high resolution yet planar techniques of standard lithography with more complex yet low resolution 3-D printing methods.

Characteristics of reactive ion etching lag in HBr/O2 plasma etching of silicon trench for nanoscale device

In this study, we investigated the etching parameter dependence of the reactive ion etch (RIE) lag of nanometer silicon trenches using HBr/O2 plasma in an inductively coupled plasma etcher. As the O2 flow rate, pressure, and source power decreased and the substrate temperature increased, the RIE lag improved. The RIE lag dependence on the O2 flow rate correlated with surface oxidation which gives rise to charging up of positive ions and reduction in silicon etching rate. Increased oxidation, rate resulted in severer RIE lag. These were verified by actinometrical optical emission spectroscopy measurements. On the other hand, the decrease in substrate temperature worsened the RIE lag owing to the remaining etching by-products deposited on the substrate. When the pressure and source power decreased, the RIE lag improved owing to the increase in average ion energy. As the bias power increased, the RIE lag improved, but for excessively high power, the RIE lag deteriorated, as the positive ions could not reach the bottom of the trench due to charging. However, the RIE lag improved at high bias powers when the RF power was pulse-modulated. There was almost no frequency dependence of the RIE lag, but the RIE lag improved when the duty ratio was reduced. The improvement of the RIE lag in the pulsed plasma is thought to be due to the relaxation of the charging up of positive ions by the negative ions generated during the power-off period.

ViPER: simulation software for high aspect ratio plasma etching of silicon

The process of pattern transfer of desired topological integrated circuits features into silicon or other semiconductor compounds plays a critical role for the production of microelectronic and photonic devices, and micro- and nanoelectromechanical systems. Any deviation from the desired shape of the pattern limits density, yield, and reliability of these devices. Gas reactivity, pressure, ion, electron, and reactant transport to the surface, and product transport away from the surface, have been identified as important issues that control the microscopic uniformity in high aspect ratio etching. A plasma etching simulation software, containing corresponding physical models, can be used to establish a link between etch process parameters such as pressure, rf power, etching gas chemistry, temperature, and the physical and chemical process parameters like energy and angular distribution of ions and neutrals, radical sticking, and surface charging. ViPER (Virtual Plasma Etch Reactor) is a full featured plasma processing simulation software developed at Ilmenau University of Technology, Department of Microelectronic and Nanoelectronic Systems (MNES) [ http://www.tu-ilmenau.de/en/mne-mns/research/plasma-etching/viper-download ]. The simulator allows a deep analysis of the most significant effects like reactive ion etching lag, charging, notching, bowing, faceting, microtrenching, profile shape dependence, and gives more insight into the physical phenomena occurring in the plasma reactor during plasma etching process, helping engineers to understand how plasma etching works.

Investigation of exhausts from fabricated silicon micronozzles with rectangular and close to rotationally symmetric cross-sections

Close to rotationally symmetric in-plane silicon micronozzles with throat and exit diameters of 45 and 260 µm, respectively, have been fabricated using semi-isotropic SF6 etching through an array mask utilizing microloading and reactive ion etching lag. Comparison with nozzles fabricated using deep reactive ion etching (DRIE) and having a rectangular cross-section but a similar hydraulic diameter in the throat, showed that the Reynolds numbers were almost equal even though the DRIE-etched nozzle had an almost five times larger cross-sectional area, hence implying less viscous losses and higher efficiency with the nearly symmetrical nozzles. The nozzle shapes have been studied using x-ray computed tomography. Comparison of the nozzles' exhaust jets using schlieren imaging, showed that the rectangular nozzles' jets deviate from the nozzle axis direction. It is believed that it is caused by the inclined side walls resulting from the DRIE etching. The results from intentionally misaligning the wafers, each containing half a nozzle, 50 µm parallel with or perpendicular to the nozzle axis, showed that the exhaust deviated and widened, respectively. The findings show that the nozzle symmetry affects both the shape and the pointing direction of the exhaust and that schlieren imaging is a powerful tool for determining nozzle thrust vector deviations.

A novel non-sequential hydrogen-pulsed deep reactive ion etching of silicon

A non-sequential pulsed-mode deep reactive ion etching of silicon is reported that employs continuous etching and passivation based on SF6 and H2 gases. The passivation layer, as an important step for deep vertical etching of silicon, is feasible by hydrogen pulses in proper time-slots. By adjusting the etching parameters such as plasma power, H2 and SF6 flows and hydrogen pulse timing, the process can be controlled for minimum underetch and high etch-rate at the same time. High-aspect-ratio features can be realized with low-density plasma power and by controlling the reaction chemistry. The so-called reactive ion etching lag has been minimized by operating the reactor at higher pressures. X-ray photoelectron spectroscopy and scanning electron microscopy have been used to study the formation of the passivation layer and the passivation mechanism.

Single Trench SiON Waveguide TE-TM Mode Converter

A TE-TM mode converter fabricated in a single trench SiON waveguide is described. The device has the advantage that only single masking and etching process is needed to fabricate it. We discuss the design of the mode converter from the view point of fabrication tolerance. The single trench structure is fabricated using the reactive ion-etch lag phenomenon. A 97% TE-TM mode conversion (extinction ratio=15 dB) is demonstrated at a wavelength of 1.27μm . An excess loss is measured to be 0.8 dB.

Two-Port Static Coated Micro Gas Chromatography Column With an Embedded Thermal Conductivity Detector

This paper reports a microfabricated 2×4 cm gas chromatography chip to separate and detect gases in a two-port structure by embedding a microthermal conductivity detector (μTCD) within a separation column. A circular on-chip heater is placed on the backside of the monolithic device enabling temperature programming and consequently faster analysis of the heavier components. A unique process enhanced by reactive ion etching lag (RIE lag) is used to achieve multiple etch depths in silicon and restrict the process flow to just three masks. The silicon substrate contains the separation column, the heater, and the tunnels for the TCD electric feed throughs. A Pyrex wafer containing the TCD elements is anodically bonded to the silicon substrate to seal the structure. Performance of a standalone μTCD fabricated in the same process and integrated in a hybrid fashion is also described. The single-chip design demonstrates successful separation and identification of multi-component gas mixtures with a performance comparable to that obtained through a flame ionization detector connected in series. Further, on-chip temperature programming capability was utilized to elevate the column temperature to 75 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C to exhibit analysis in less than a minute.

A triple-layer protection process for high-aspect-ratio silicon micromachining by DRIE of SOI substrates

Using the buried oxide layer of silicon-on-insulator (SOI) wafers as the etch-stop layer, a triple-layer protection process integrating deep reaction ion etching (DRIE) and wet anisotropic bulk micromachining is demonstrated to fabricate various three-dimensional MEMS devices on SOI wafer. Several limitations of the DRIE process, including bottom grass formation, reactive ion etching lag and notching effects, are solved by modifying the process parameters to achieve satisfactory performance. This process is capable of various applications and is applied to fabricate a resonant pressure sensor in this study. In summary, the developed process possesses most existing merits and reduces many design constraints of the existing high-aspect-ratio micromachining process, contributing to a more competitive and convenient micromachining.

Ultracompact polarization converter with a dual subwavelength trench built in a silicon-on-insulator waveguide

The design and fabrication of an ultracompact silicon-on-insulator polarization converter is reported. The polarization conversion with an extinction ratio of 16 dB is achieved for a conversion length of only 10 μm. Polarization rotation is achieved by inducing a vertical asymmetry by forming in the waveguide core two subwavelength trenches of different depths. By taking advantage of the calibrated reactive ion etch lag, the two depths are implemented using a single mask and etching process. The measured converter loss is -0.7 dB and the 3 dB bandwidth is 26 nm.

Dry Etching of Al-Rich AlGaAs for Photonic Crystal Fabrication

We investigate inductively coupled plasma deep dry etching of Al0.8Ga0.2As for photonic crystal (PC) fabrication using Cl2, BCl3, and CH4 chemistry. The characteristic AlOx deposition is observed during the etching, resulting in the reduction of etching rate. BCl3 is considered to scavenge the deposited AlOx by its reductive reaction. CH4 passivates the etching sidewall, as well as enhances the deposition of AlOx. Concerning the impact of pattern size, a pronounced inverse reactive ion etching (RIE) lag is observed, which is beneficial for small-size PC fabrication typically with a hole diameter of 100–500 nm. From the findings, we successfully fabricated a PC structure with air holes having an aspect ratio of 8 and a diameter of 110 nm.

Atomic-Scale Cellular Model and Profile Simulation of Si Etching: Analysis of Profile Anomalies and Microscopic Uniformity

Reactive ion etching (RIE) has been used in the manufacture of semiconductor integrated circuit devices. However, the formation mechanisms of profile anomalies and microscopic uniformity have been poorly understood until now. In this paper, we focus on the analysis of formation mechanisms of profile anomalies and microscopic uniformity during plasma etching of Si in Cl2 plasmas, using our own atomic-scale cellular model (ASCeM). The numerical results indicated that high neutral-to-ion flux ratios result in microtrench formation. Moreover, RIE lag tends to occur at low neutral-to-ion flux ratios (<50), whereas inverse RIE lag occurs at high neutral-to-ion flux ratios in typical low-pressure and high-density plasmas. In particular, the etch rates for narrow patterns (<70 nm) increase significantly with increasing neutral-to-ion flux ratio. The synergistic effects between ion-enhanced etching and neutral shadowing in microstructural features play a significant role in the formation of profile anomalies.

A fabrication technology for three-dimensional micro total analysis systems

This paper presents a new fabrication technique capable of creating three-dimensional (3D) buried microchannels in a silicon substrate. With a single mask and a single etch of the substrate, silicon microstructures are created with control in all three dimensions by utilizing reactive ion etch (RIE) lag. The microstructures are then sealed with plasma enhanced chemical vapor deposition (PECVD) dielectrics. By depositing up to 6.3 µm of PECVD oxide, rectangular openings in the masking layer ranging in size from 2 µm × 2 µm to 4 µm × 10 µm microchannels were sealed. Using these mask openings, microchannels were created with depths ranging from 4 µm to 200 µm. In addition channels with controlled transition between depths and transition slopes ranging from 40° and 60° were created. Furthermore, the flexibility of this technique allows for the creation of predictable nano-scaled holes on the substrate surface. The entire process is fabricated on silicon and CMOS compatible, thus allowing for 3D buried channel devices to be integrated with microelectronics. To show the impact of this technique, practical microfluidic devices with a wide range of applications are demonstrated.