A fabrication technology for three-dimensional micro total analysis systems

Abstract

This paper presents a new fabrication technique capable of creating three-dimensional (3D) buried microchannels in a silicon substrate. With a single mask and a single etch of the substrate, silicon microstructures are created with control in all three dimensions by utilizing reactive ion etch (RIE) lag. The microstructures are then sealed with plasma enhanced chemical vapor deposition (PECVD) dielectrics. By depositing up to 6.3 µm of PECVD oxide, rectangular openings in the masking layer ranging in size from 2 µm × 2 µm to 4 µm × 10 µm microchannels were sealed. Using these mask openings, microchannels were created with depths ranging from 4 µm to 200 µm. In addition channels with controlled transition between depths and transition slopes ranging from 40° and 60° were created. Furthermore, the flexibility of this technique allows for the creation of predictable nano-scaled holes on the substrate surface. The entire process is fabricated on silicon and CMOS compatible, thus allowing for 3D buried channel devices to be integrated with microelectronics. To show the impact of this technique, practical microfluidic devices with a wide range of applications are demonstrated.