Clock Frequency Research Articles

DMA controller design based on SHA-1 dual channel improvement algorithm

In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects.

Energy-Aware Partitioned Scheduling of Imprecise Mixed-Criticality Systems

We consider partitioned scheduling of an Imprecise Mixed-Criticality (IMC) taskset on a uniform multiprocessor platform, with Earliest Deadline First-Virtual Deadline (EDF-VD) as the uniprocessor task scheduling algorithm, and address the optimization problem of finding a feasible task-to-processor assignment and low-criticality (LO) mode processor speed with the objective of minimizing the system’s average energy consumption in LO mode. We propose a task-to-processor assignment algorithm Criticality-Unaware Worst-Fit Decreasing (CU-WFD) algorithm, which allocates tasks with the Worst-Fit Decreasing (WFD) heuristic method based on utilization values at their respective criticality levels. We determine the energy-efficient speed for each processor based on EDF-VD scheduling, and present our algorithm Energy-Efficient Partitioned Scheduling for Imprecise Mixed-Criticality (EEPSIMC) with the CU-WFD heuristic algorithm to minimize system energy consumption. The experimental results show that our proposed algorithm has good performance in terms both schedulability ratio and normalized energy consumption compared to seven comparison baselines.

A two-process model of Drosophila sleep reveals an inter-dependence between circadian clock speed and the rate of sleep pressure decay.

Sleep is controlled by two processes-a circadian clock that regulates its timing and a homeostat that regulates the drive to sleep. Drosophila has been an insightful model for understanding both processes. For four decades, Borbély and Daan's two-process model has provided a powerful framework for understanding sleep regulation. However, the field of fly sleep has not employed such a model as a framework for the investigation of sleep. To this end, we have adapted the two-process model to the fly and established its utility by showing that it can provide empirically testable predictions regarding the circadian and homeostatic control of fly sleep. We show that the ultradian rhythms previously reported for loss-of-function clock mutants in the fly are robustly detectable and a predictable consequence of a functional sleep homeostat in the absence of a functioning circadian system. We find that a model in which the circadian clock speed and homeostatic rates act without influencing each other provides imprecise predictions regarding how clock speed influences the strength of sleep rhythms and the amount of daily sleep. We also find that quantitatively good fits between empirical values and model predictions were achieved only when clock speeds were positively correlated with rates of decay of sleep pressure. Our results indicate that longer sleep bouts better reflect the homeostatic process than the current definition of sleep as any inactivity lasting 5 minutes or more. This two-process model represents a powerful framework for work on the molecular and physiological regulation of fly sleep.

Efficient Hardware Implementation of Elliptic-Curve Diffie–Hellman Ephemeral on Curve25519

Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular addition, subtraction, multiplication, and inversion. Our proposed hardware architecture enhances the efficiency of ECDHE operations while maintaining low resource utilization, considerably reduced latency, and low power consumption. Synthesized on the Xilinx Artix-7 platform, our design boasts 64,000 Slices and a clock speed of 102 MHz, and it computes an ECDHE scalar multiplication operation in 1.1 ms, consuming 117 mW. The proposed hardware design can be applied to various platforms, including mobile devices and IoT systems.

A Reconfigurable 4th Order IIR Filter For The Low Frequency Applications

Huge numbers of advanced electrical engineering applications employ infinite impulse response (IIR) filters very frequently in order to meet market’s demands. Especially, some applications such as video processing, digital signal processing and high-speed digital communication necessitate computational efficiency and low latency. In this point of view, high-speed processing of digital data require a digital signal processor or an FPGA instead of a conventional microprocessor. In this respect, in the last decades, FPGAs are commonly used in order to bring new opportunities to the designers. This work gives a FPGA hardware design of a 4th order IIR reconfigurable filter structure. The proposed filter’s maximum clock frequency is around 32MHz which covers different low frequency applications from biomedical signal processing up to speech applications. To verify the performance of the filter, 4th order Butterworth and Chebyshev filters are realized in the basis of Matlab results and FPGA behavioral model. Also, consuming logic gates and blocks are given in order to evaluate chip area occupation. It should be considered that the proposed filter scheme presents promising results to meet low frequency applications.

Remote Residual Instability Evaluation of Comb-Based Precise Frequency Transmission for Optical Clock

Optical clocks can be used as the absolute frequency reference due to their high accuracy and stability. In a precise optical clock transmission system, the instability loss of the link is usually evaluated by beating the remote optical signal with the reference clock, which is not suitable for real frequency distribution applications. Therefore, it is necessary to assess the performance directly at the remote site for the optical frequency transfer, because the two sites of the link are usually not co-located. In this paper, we proposed a comb-based remote residual instability evaluation scheme. Two coherent optical combs with different wavelengths were extracted from a frequency stable comb and transmitted after multiplexing. The residual instability was evaluated directly at the remote site by measuring the phase fluctuation difference between the two combs. We achieved 8.61 × 10−19 at 40,000 s over a 10 km fiber link, reaching the instability of optical clocks. These results revealed that our scheme can evaluate optical clock frequency transmission directly at the remote site, which made the method truly practical.

Research on the Application and Performance Optimization of GPU Parallel Computing in Concrete Temperature Control Simulation

With the development of engineering technology, engineering has higher requirements for the accuracy and the scale of simulation calculation. The computational efficiency of traditional serial programs cannot meet the requirements of engineering. Therefore, reducing the calculation time of the temperature control simulation program has important engineering significance for real-time simulation of temperature field and stress field, and then adopting more reasonable temperature control and crack prevention measures. GPU parallel computing is introduced into the temperature control simulation program of massive concrete to solve this problem and the optimization is carried out. Considering factors such as GPU clock rate, number of cores, parallel overhead and Parallel Region, the improved GPU parallel algorithm analysis indicator formula is proposed. It makes up for the shortcomings of traditional formulas that focus only on time. According to this formula, when there are enough threads, the parallel effect is limited by the size of the parallel domain, and when the parallel domain is large enough, the efficiency is limited by the parallel overhead and the clock rate. This paper studies the optimal Kernel execution configuration. Shared memory is utilized to improve memory access efficiency by 155%. After solving the problem of bank conflicts, an accelerate rate of 437.5× was realized in the subroutine of the matrix transpose of the solver. The asynchronous parallel of data access and logical operation is realized on GPU by using CUDA Stream, which can overlap part of the data access time. On the basis of GPU parallelism, asynchronous parallelism can double the computing efficiency. Compared with the serial program, the accelerate rate of inner product matrix multiplication of the GPU asynchronous parallel program is 61.42×. This study further proposed a theoretical formula of data access overlap rate to guide the selection of the number of CUDA streams to achieve the optimal computing conditions. The GPU parallel program compiled and optimized by the CUDA Fortran platform can effectively improve the computational efficiency of the simulation program for concrete temperature control, and better serve engineering computing.

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic design automation (EDA) tools like Synopsys, and Cadence to carry out accurate chip verification. However, when using a licensed EDA tool, it is difficult to change the function and confirm the overall process in detail. If the design is wrong, the expected cost is doubled, as it will be necessary to modify the design and check all processes for verification. Currently, it cannot check the synthesizability of the clock tree on the placement and route process using only RTL. The main purpose of this study is to predict the CTS result of pre-estimation roughly using an RTL source placing temporary logics using random buffer insertion before the route process: then the incorrectly designed part can be freely modified because the CTS result can be known in advance. Experimental results showed that this research achieves an increase in inserted buffer area by about 10%, the standard deviation of clock skew achieves zero clock skew after shallow CTS, and clock frequency increases by about 10%. This paper contributes to optimizing clock tree implementation by conducting the pre-route process before using the CTS tool. Also, our approach not only minimizes resource usage but also optimizes CTS for the RTL structure. It holds considerable value in enhancing the efficiency and performance of integrated circuits.

Diurnal variation of monsoon winds during the onset, active-break and withdrawal phases observed at its gateway in India: A case study of 2021

Diurnal variation of the low-level jet (LLJ) and tropical easterly jet stream (TEJ) over Cochin – the gateway of Indian summer monsoon – was investigated during the monsoon onset over Kerala (MOK), active-break, and withdrawal phases in the year 2021. Horizontal wind profiles obtained from the 205 MHz wind profiling radar at Cochin University of Science and Technology, India, were analyzed to delineate the core speed and core heights of the LLJ and TEJ. Distinct diurnal variability in wind patterns was observed during various monsoon phases. The LLJ and TEJ core speed and heights exhibited significant diurnal variations, with the LLJ reaching maximum diurnal amplitudes between 2.5 m s−1 (onset phase) and 0.5 m s−1 (break phase). Notably, the LLJ core speed during the break phase was approximately half of that during the active phase. The ratios of the diurnal range to the time mean LLJ core speed varied between 0.19 (active phase) and 1.33 (onset phase). Moreover, the LLJ core height is higher during active compared to break. Similarly, the TEJ core height at Cochin is marginally higher during active compared to that during break. Interestingly, an enhanced TEJ core speed and weakened LLJ were observed during the break phases. The variation of moisture flux exhibited positive correlation with the core speed with 2–3 h lag, significantly influencing the diurnal variability of rainfall. The causative factors behind the diurnal oscillations during various phases of the monsoon are discussed.

Design of automatic tobacco trash detection system based on quadratic fuzzy theory

Abstract Fuzzy sets and deep learning models have accurate recognition accuracy in automatic detection. To be able to accurately identify tobacco debris and improve the quality of cigarettes, this paper proposes the design of a tobacco debris detection system with a deep learning model and fuzzy quadratic theory. The collected data is stored to AL422B by quadratic fuzzy set timing conversion, the cached image data is read by the microcontroller, the image pixel points are output, and the external controller and internal registers are set to read the tobacco image. The integrated Thumb extended instruction set to obtain the CPU clock frequency makes the controller interrupt and ensures PWM output. Integrate the internal fixed oscillator and external integrated control circuit to debug the program interface circuit to prevent power on and off misoperation. The negative log-likelihood function is obtained by following the activation rules given by the visible layer and hidden layer activation functions. The RBM is trained by quadratic fuzzy set estimation to optimize the parameters; test sample sets appear overfitting, combined with DBN pre-training and fine-tuning, iterative output, and labeling target data to meet the preset requirements to achieve intelligent detection of tobacco debris. The result analysis shows that the deep learning model and the quadratic fuzzy set generalization ability and accuracy are high, the highest F-value in tobacco clutter detection reaches 100%, and the system is designed to detect tobacco clutter automatically with high accuracy and good detection of clutter.

Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification

The Tsetlin Machine (TM) is a machine learning algorithm based on an ensemble of Tsetlin Automata (TAs) that learns propositional logic expressions from Boolean input features. In this paper, the design and implementation of a Field Programmable Gate Array (FPGA) accelerator based on the Convolutional Tsetlin Machine (CTM) is presented. The accelerator performs classification of two pattern classes in 4 × 4 Boolean images with a 2 × 2 convolution window. Specifically, there are two separate TMs, one per class. Each TM comprises 40 propositional logic formulas, denoted as clauses, which are conjunctions of literals. Include/exclude actions from the TAs determine which literals are included in each clause. The accelerator supports full training, including random patch selection during convolution based on parallel reservoir sampling across all clauses. The design is implemented on a Xilinx Zynq XC7Z020 FPGA platform. With an operating clock speed of 40 MHz, the accelerator achieves a classification rate of 4.4 million images per second with an energy per classification of 0.6 μJ. The mean test accuracy is 99.9% when trained on the 2-dimensional Noisy XOR dataset with 40% noise in the training labels. To achieve this performance, which is on par with the original software implementation, Linear Feedback Shift Register (LFSR) random number generators of minimum 16 bits are required. The solution demonstrates the core principles of a CTM and can be scaled to operate on multi-class systems for larger images.

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

A pseudo-random binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both, the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77 GHz clock frequency, and the ERSFQ variant up to 45.72 GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ).

A 1.25-GHz multi-amplitude modulator driver in 0.18 μm SiGe BiCOMOS technology for high speed quantum key distribution.

Quantum key distribution (QKD) research has yielded highly fruitful results and is currently undergoing an industrialization transformation. In QKD systems, electro-optic modulators are typically employed to prepare the required quantum states. While various QKD systems operating at GHz repetition frequency have demonstrated exceptional performance, they predominantly rely on instruments or printed circuit boards to fulfill the driving circuit function of the electro-optic modulator. Consequently, these systems tend to be complex with low integration levels. To address this challenge, we have introduced a modulator driver integrated circuit in 0.18 µm SiGe BiCMOS technology. The circuit can generate multiple-level driving signals with a clock frequency of 1.25GHz and a rising edge of ∼50ps. Each voltage amplitude can be independently adjusted, ensuring the precise preparation of quantum states. The measured signal-to-noise ratio was more than 17 dB, resulting in a low quantum bit error rate of 0.24% in our polarization-encoding system. This work will contribute to the advancement of QKD system integration and promote the industrialization process in this field.

Using All-Digital On-Chip Syntonistor to Compensate Clock Frequency Error in Network Time Synchronization for Accuracy Reaching to Sub-µs Range

The emergence of Internet of Everything has made time-awareness a feature of high priority. One of the enabling factors is time synchronization. High quality synchronization demands frequency source of high stability, which is pricey and bulky. When low-end source is used, synchronization quality would be severely impaired. This situation can be improved by the technique of time synchronization. In mainstream approaches, however, the frequency of clock pulse train is not tuned due to the lack of appropriate tool. As requirement for synchronization advances into microsecond or even nanosecond regime, frequency tuning in hardware is expected to be beneficial. Moreover, wireless networks do not have frequency transfer mechanism. This exacerbates the problem of frequency deviation. Those issues make syntonization (synchronization of frequency) become necessary. In this work, an all-digital frequency-tunable clock source is used as on-chip syntonistor to physically compensate the clock frequency errors of nodes in a network. Time discrepancies are hence alleviated. A wireless network has been built to validate this scheme. Time synchronization quality has reached to sub-µs range. The key contribution is the suggestion of adopting on-chip syntonistor for improving the quality of network synchronization. This work serves as a demonstration of this new scheme.

The influence of the cooling system on the efficiency of thermal management and the performance of computer components

The article attempts to evaluate the existing methods of cooling computer components in terms of ensuring their efficient operation. Issues related to heat exchange were discussed and individual computer components were characterized in terms of heat reception and the available methods of cooling computer components were reviewed. Based on the analysis of cooling methods, the most appropriate solution was selected in terms of: efficiency, costs and generated noise. A liquid cooling system was designed for the model computer, allowing for a significant increase in the clock speed of the computer’s main components. In order to determine the efficiency of the system, i.e. the maximum flow that can be discharged by the system, and to determine the efficiency of the required coolers, appropriate calculations were made regarding: thermal conductivity between each of the cooled elements and the corresponding block and heat transfer to the cooling liquid inside each of the blocks.

DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs

Brain-inspired spiking neural networks (SNNs) replace the multiply-accumulate operations of traditional neural networks by integrate-and-fire neurons, with the goal of achieving greater energy efficiency. Specialized hardware implementations of those neurons clearly have advantages over general-purpose devices in terms of power and performance, but exhibit poor scalability when it comes to accelerating large neural networks. DeepFire2 introduces a hardware architecture which can map large network layers efficiently across multiple super logic regions in a multi-die FPGA. That gives more control over resource allocation and parallelism, benefiting both throughput and energy consumption. Avoiding the use of lookup tables to implement the <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AND</monospace> operations of an SNN, prevents the layer size to be limited by logic resources. A deep pipeline does not only lead to an increased clock speed of up to 600 MHz. We double the throughput and power efficiency compared to our previous version of DeepFire, which equates to an almost 10-fold improvement over other previous implementations. Importantly, we are able to deploy a large ImageNet model, while maintaining a throughput of over 1500 frames per second.

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

Fusion of powerful features of Harris Hawks with Cuckoo Search algorithm for engineering applications

The High-level synthesis (HLS) is a key step in the digital VLSI circuit design. HLS can be seen in the present study as an important matter of intelligently map a Data Flow Graph (DFG) specification of digital filters to FPGA. In this article, the powerful features of the Harris hawks optimization (HHO) and Cuckoo search (CS) algorithm have improved the performance of the proposed method. This proposed strategy is also known as the GChO algorithm. In GChO, the phase of CS helps to force the HHO to escape from stagnation, to ignore local optima and premature convergence. In addition for HLS, the three retiming-based models were also proposed in the work. The standard pipelining was employed in Model 1. The modified Min-Period Retiming on the multiplier less digital filters was incorporated by Model 2 and led to a significant improvement in clock frequency. Model 3 adopted modified Min-Area Retiming on digital filters and reduced the complexity of the circuit; however these designs therefore offer single parameter-based heuristic solution. This can be resolved by using meta-heuristic approach focused on retiming. The use of meta-heuristic methods and swarm intelligence has been considered as a highly desirable choice when searching the digital block solution space with higher frequency and reduced complexity in HLS problems. The robustness of the GChO method has been verified on IEEE CEC’ 2020 standard benchmark test suites. The paper analyzes that the performance of the proposed GChO algorithm outperforms the Harris hawks optimization (HHO), Moth Flame optimization algorithm, Particle Swarm optimization algorithm, Chimp optimization algorithm for the HLS digital filters. The experimental results show that the proposed Model 2 and 3 for retimed PDR-FIR filter is improved in term of MUF by 7.38% and utilized slices by 37.77%, PRO-DFII IIR retimed filter by 10.54%, and complexity reduced by 29.69%, PRO-LAT-ARF by 41.61% and slice by 11.17% and PRO-LATLAD-IIR improved in term of MUF, slices by 35.69% and 38.095% in relative to the standard retimed filters of various architecture. For the evolutionary GChO-retimed filter, an improvement in MUF by 58.52%, and utilized slices by 49.61%, for PDR-FIR, 48.09%, 80.76% for PRO-DFII-IIR , 52.68%, 54.33% for PRO-LAT-ARF, 27.85% and 18.46% for PRO-LATLAD-IIR are achieved in respect of Model 2 and 3 whereas an improvement in term of MUF by 34.60%, and utilized slices by 37.61%, for PDR-FIR, 40.55%, 39.66% for PRO-DFII-IIR, 40.08%, 31.33% for PRO-LAT-ARF, 26.95%, 24.41% for PRO-LATLAD-IIR are achieved with respect of other meta-heuristic methods.

Design and Implementation of an Internet-of-Things-Enabled Smart Meter and Smart Plug for Home-Energy-Management System

The demand response program is an important feature of the smart grid. It attempts to reduce peak demand, improve the smart grid efficiency, and ensure system reliability. Implementing demand-response programs in residential and commercial buildings requires the use of smart meters and smart plugs. In this paper, we propose an architecture for a home-energy-management system based on the fog-computing paradigm, an Internet-of-Things-enabled smart plug, and a smart meter. The smart plug measures in real-time the root mean square (RMS) value of the current, frequency, power factor, active power, and reactive power. These readings are subsequently transmitted to the smart meter through the Zigbee network. Tiny machine learning algorithms are used at the smart meter to identify appliances automatically. The smart meter and smart plug were prototyped by using Raspberry Pi and Arduino, respectively. The smart plug’s accuracy was quantified by comparing it to laboratory measurements. To assess the speed and precision of the small machine learning algorithm, a publicly accessible dataset was utilized. The obtained results indicate that the accuracy of both the smart meter and the smart plug exceeds 97% and 99%, respectively. The execution of the trained decision tree and support vector machine algorithms was verified on the Raspberry Pi 3 Model B Rev 1.2, operating at a clock speed of 600 MHz. The measured latency for the decision tree classifier’s inference was 1.59 microseconds. In a practical situation, the time-of-use-based demand-response program can reduce the power cost by about 30%.