64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

Abstract

A pseudo-random binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both, the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77 GHz clock frequency, and the ERSFQ variant up to 45.72 GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ).