Rapid Single Flux Quantum Circuits Research Articles

Surface Inductance of Superconductive Striplines

Inductance in superconductive circuits plays a significant role in rapid single flux quantum (RSFQ) systems. Inductance estimation is a challenging issue. The microwave behavior of these inductances is characterized by the surface inductance of a line. A methodology to accurately estimate the surface inductance of a stripline is the focus of this brief. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is provided. The effects of process parameter variations on the surface inductance are also discussed. An expression to model the effects of the trapezoidal geometry of a stripline is presented. The dependence of the surface inductance on the oxide and metal layer thicknesses is also presented. The objective is to provide an accurate estimate of the surface inductance for use in automated routing of VLSI complexity RSFQ circuits.

VWSIM: A Circuit Simulator

VWSIM is a circuit simulator for rapid, single-flux, quantum (RSFQ) circuits. The simulator is designed to model and simulate primitive-circuit devices such as capacitors, inductors, Josephson Junctions, and can be extended to simulate other circuit families, such as CMOS. Circuit models can be provided in the native VWSIM netlist format or as SPICE-compatible netlists, which are flattened and transformed into symbolic equations that can be manipulated and simulated. Written in the ACL2 logic, VWSIM provides logical guarantees about each of the circuit models it simulates. Note, our matrix solving and evaluation routines use Common Lisp floating-point numbers, and work is ongoing to admit these models into ACL2. We currently use VWSIM to help us design self-timed, RSFQ-based circuits. Our eventual goal is to prove properties of RSFQ circuit models. The ACL2-based definition of the VWSIM simulator offers a path for specifying and verifying RSFQ circuit models.

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-box circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

Thermal Modeling of Rapid Single Flux Quantum Circuit Structures

The operation of rapid single flux quantum (RSFQ) circuits depends upon the superconductive properties of the Josephson junctions (JJs) and metal layers, which are highly dependent on the temperature. Increasing densities and frequencies of JJs in RSFQ circuits have created a need to accurately model the local ambient thermal environment. In this article, an analytic thermal model of RSFQ circuit structures targeting the MIT Lincoln Laboratory SFQ5ee 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> technology is presented. The model is based on a network of thermal resistances, representing the heat generation and thermal paths within an RSFQ circuit. An error of less than 0.22% between the model and a numerical solver is achieved. To reduce the computational complexity, the sparsity of the matrix of thermal resistances among the nodes is increased by exploiting the effective radius of the heat spreading behavior. Ignoring the thermal effects of the heating elements outside of a target radius reduces the number of thermal resistances by 50%, increasing the maximum error of the model to only 0.26%.

Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered as one promising technology in superconducting digital applications. In this article, given the placement result of a multiple-stage pipelined architecture with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> gate columns and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> gate components in an RSFQ circuit inside a rectangular layout, it is assumed that signals can be propagated from the primary inputs on the left boundary to the primary outputs on the right boundary. First, a lower bound on the routed width of one PTL region can be defined as the estimated width of one PTL region. Furthermore, the sum of the estimated widths of all the PTL regions in an RSFQ circuit can be defined as the estimated region width in an RSFQ circuit and the estimated width can be used as the objective function for the design of the clock distribution in an RSFQ circuit. Based on the flexibility of using the clock splitters (SPLs) inside the gate components for the propagation of clock signals, an iterative assignment algorithm can be proposed to complete the assignment of the tree-based clock connections with minimizing the estimated width of an RSFQ circuit. From viewpoint of numerical experiments, the experimental results show that the reduction of the estimated region width can lead to the reduction of the final width of the PTL regions in an RSFQ circuit. Compared with the design of Kito’s tree-based clock distribution for 5 tested RSFQ circuits, the experimental results show that the design of our proposed tree-based clock distribution with two capability parameters, 2 and 3, on a clock SPL can use reasonable CPU time to reduce 47.03% and 54.33% of the estimated region width and 44.83% and 45.25% of the final width for 5 tested RSFQ circuits on the average, respectively.

Application of Phase-Based Circuit Theory to RSFQ Logic Design

In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.

Splitter Trees in Single Flux Quantum Circuits

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made the issue of multiple fanout of growing importance. Most RSFQ gates can only drive a single output. Splitter gates can however distribute an SFQ pulse to multiple fanout. To drive N SFQ gates, N-1 splitters with a fanout of two are required. Large splitter trees are often used in high speed VLSI complexity SFQ systems. These splitters require significant area and increase the path delay. In this paper, three area and power efficient splitter topologies for large scale RSFQ circuits are introduced. These SFQ splitters are an active splitter tree with fewer JJs, a passive splitter, and a multi-output active splitter. A methodology is presented for determining when to use passive or active splitters. Tradeoffs among the number of JJs, bias current of each stage, and delay are reported along with a margin analysis. The proposed splitters greatly reduce the required bias currents and delay of large scale RSFQ circuits by enabling multiple fanout. The methodologies and techniques are applicable to automated layout and clock tree synthesis for large scale SFQ integrated circuits.

Demonstration of Interface Circuits Between Half- and Single- Flux- Quantum Circuits

We demonstrated interface circuits between a half-flux-quantum (HFQ) circuit and a rapid single-flux-quantum (RSFQ) circuit to obtain SFQ/HFQ and HFQ/SFQ converters. These converters were created by simply inserting a resistor between an RSFQ circuit and the adjacent HFQ circuit, where both circuits are based on pulse logic. These converters enable us to create combinatory circuits that make the best use of the features of the two circuits. Using a DC/SFQ, SFQ/HFQ, HFQ/SFQ, and SFQ/DC converter, we measure an HFQ Josephson transmission line (JTL) composed of eight 0-0-π superconducting quantum interference devices (SQUIDs), which are the essential elements of an HFQ circuit. The 0-0-π SQUIDs are composed of two conventional Josephson junctions and a π-shifted ferromagnetic junction. The HFQ JTL demonstrated in this study is driven by a bias current 11-fold lower than that of a similar RSFQ JTL. These experimental results indicate that the HFQ circuit requires power that is two or more orders of magnitude lower than that of an RSFQ circuit.

Research On Power Dissipation of ERSFQ Circuits

Energy-efficient rapid single flux quantum (ERSFQ) circuits are often considered to have two working states including ERSFQ (zero static power dissipation) and RESFQ (resistive energy-efficient SFQ) state. In our previous research, a new working state called MIDSFQ state has been also found in which the biasing JJs cannot return to the non-voltage state after the dynamic process. Both the RESFQ and MIDSFQ states result in extra power dissipation and should be avoided if possible. In this paper, we investigate the characteristics of these three states and explain the working principle of the MIDSFQ state using the hysteresis effect. We obtain an optimization scenario to eliminate the MIDSFQ state and furthermore, a simple but effective method to improve power efficiency of ERSFQ circuits.

A Compact Interface Between Adiabatic Quantum-Flux-Parametron and Rapid Single-Flux-Quantum Circuits

Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits

Rapid single-flux-quantum (RSFQ) circuits are developing rapidly, but there are still many layouts that need to be completed manually, greatly reducing the design efficiency. We report the shape constraints of Josephson transmission line (JTL), and then propose automatic placement and routing methods for RSFQ circuits. First, for the pipeline structure of concurrent-flow clocking, a detailed placement algorithm based on simulated annealing is proposed, which use D Flip-Flop (DFF) insertion, column placement, and intra-column perturbation strategies to ensure the synchronization of clock phase while completing the placement of logic cells. More importantly, for the shape constraints of JTL, a new two-step JTL routing method is proposed. The first step is dummy wire routing, and the shape violations and routing congestion caused by shape constraints are solved to search legal paths for JTL routing; in the second step, timing optimization is performed when replacing dummy wire with JTL cells. Experimental results show that the proposed automatic methods achieve a 5% area-reduction and a 20× speed-up compared to manual design.

25-GHz Operation of ERSFQ Time-to-Digital Converter

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits

Aided by the advancement of super-conductive materials, rapid single flux quantum (RSFQ) digital circuits are emerging as a promising complement or even replacement of the traditional CMOS digital integrated circuits. RSFQ digital circuits typically work at a low temperature of around 4.2 K, i.e., around −268.95 °C. Nevertheless, the operating frequency of RSFQ digital circuits reaches up to 770 GHz, which is orders of magnitudes faster than contemporary CMOS digital circuits. The high operating frequency causes critical design challenges especially for the clock networks and data path signals, where relative skew on wires need to be observed for achieving the correct functionality. Therefore, for designing a timing-variability-aware SFQ layout, it is necessary to match the PTL delays that are proportional to their respective lengths. And the matching of PTL delays should be carried out by extensions in PTL lengths. To meet the above-mentioned critical timing requirements, it is necessary to incorporate length-matching constraints into a routing problem, which is transformed from the timing requirements of matching the PTL delays during the logical synthesis stage. However, existing routing algorithms are inherently limited by preallocated splitters (SPLs), which complicates the subsequent routing stage under length-matching constraints. In this article, in order to effectively address the length-matching constraints, we reallocate SPLs to fully utilize routing resources. We propose the first multiterminal routing algorithm for RSFQ circuits, which integrates SPL reallocation into the routing stage and achieves 100% routing completion in the tested benchmarks. Compared with the state-of-the-art method, the proposed multiterminal routing algorithm reduces the required area by 17% and the runtime by 7%.

Repeater Insertion in SFQ Interconnect

Superconductive passive transmission lines (PTL) are widely used for signal routing in large-scale rapid single flux quantum (RSFQ) circuits. Due to the imperfect matching of the transmission lines between the driver and receiver, single flux quantum (SFQ) pulses are partially reflected. The round trip propagation time of these reflections can coincide with the following SFQ pulse, resulting in a decrease in bias margins or incorrect circuit behavior. This resonant effect depends upon the length of the PTL and the clock frequency of the signal. A methodology to reduce and manage this effect is the focus of this article. A closed-form expression describing the dependence of the resonance frequency on the length of the PTL is presented. This expression describes a set of forbidden lengths for PTL interconnect segments in RSFQ circuits. The proposed methodology and algorithm insert active PTL-based repeaters into long superconductive interconnect while ensuring the length of the line segment is outside the forbidden region and increasing bias margins.

Design Methodology for Distributed Large-Scale ERSFQ Bias Networks

Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors, while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements—current limiting Josephson junctions, bias inductors, and feeding Josephson transmission lines (FJTLs). In this article, parameter guidelines and design techniques for ERSFQ circuits are presented. The proposed guidelines enable more robust circuits resistant to severe variations in supplied bias currents. Trends are considered, and advantageous tradeoffs are discussed for the different components within a bias network. The guidelines provide a means to decrease the size of an FJTL and, thereby, reduce the physical area, power dissipation, and overall bias currents, supporting further increases in circuit complexity. A distributed approach to ERSFQ FJTL is also presented to simplify placement and minimize the effects of the parasitic inductance of the bias lines. This methodology and related circuit techniques are applicable to automating the synthesis of bias networks to enable large-scale ERSFQ circuits.

Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

Measurement of Inductance in Niobium Nitride Films for Single Flux Quantum Circuits

In recent years, rapid single flux quantum (RSFQ) circuits, which are promising for the development of high-speed digital electronics, have attracted widespread interest. Niobium nitride (NbN) films have also attracted significant attention for high-frequency applications in superconducting electronics because of their superior material parameters, including their high critical temperature T c and large gap voltage V g. To enable the development of all-NbN SFQ circuits, we have developed a fabrication process based on NbN junctions and inductors made of NbN strip lines. It is important to evaluate the inductance because it can affect the performance of an RSFQ circuit and is essential for the RSFQ design. We measured the inductance properties of both epitaxial and polycrystalline NbN strip lines using a superconducting quantum interference device modulation technique at 4.2 K and obtained the width dependence on the inductance of the NbN films. The penetration depth was then calculated from these measurements. The NbN inductance values were calculated numerically with respect to the penetration depth and were then compared with the measured values from the experiments. It was demonstrated that the differences between these values were within 5%. The results reported here will be useful for the design and fabrication of all-NbN RSFQ circuits.

Fast RSFQ and ERSFQ Parallel Counters

Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums seven inputs has been designed and tested at the target clock frequency of 40 GHz and at frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output at the same target frequency was designed by combining 2 variants of 8-to-4 parallel counters. The first variant based on the 7-to-3 parallel counter, sums eight unweighted inputs, whereas the second variant sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.

Asynchronous Dynamic Single-Flux Quantum Majority Gates

Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.

ERSFQ Power Delivery: A Self-Consistent Model/Hardware Case Study

Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.