Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits

Abstract

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered as one promising technology in superconducting digital applications. In this article, given the placement result of a multiple-stage pipelined architecture with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> gate columns and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> gate components in an RSFQ circuit inside a rectangular layout, it is assumed that signals can be propagated from the primary inputs on the left boundary to the primary outputs on the right boundary. First, a lower bound on the routed width of one PTL region can be defined as the estimated width of one PTL region. Furthermore, the sum of the estimated widths of all the PTL regions in an RSFQ circuit can be defined as the estimated region width in an RSFQ circuit and the estimated width can be used as the objective function for the design of the clock distribution in an RSFQ circuit. Based on the flexibility of using the clock splitters (SPLs) inside the gate components for the propagation of clock signals, an iterative assignment algorithm can be proposed to complete the assignment of the tree-based clock connections with minimizing the estimated width of an RSFQ circuit. From viewpoint of numerical experiments, the experimental results show that the reduction of the estimated region width can lead to the reduction of the final width of the PTL regions in an RSFQ circuit. Compared with the design of Kito’s tree-based clock distribution for 5 tested RSFQ circuits, the experimental results show that the design of our proposed tree-based clock distribution with two capability parameters, 2 and 3, on a clock SPL can use reasonable CPU time to reduce 47.03% and 54.33% of the estimated region width and 44.83% and 45.25% of the final width for 5 tested RSFQ circuits on the average, respectively.