Gate Bias Range Research Articles

A new quasi-2-D model for hot-carrier band-to-band tunneling current

A significant mismatch occurs when we predict the gate-induced drain leakage current (GIDL) by using existing one-dimensional (l-D) models. It's found that the gate-induced drain leakage current is attributed to not only the vertical field but also the lateral field near the drain-to-gate overlap region. Therefore, a new quasi-two-dimensional (quasi-2-D) model considering both the lateral and vertical fields for predicting the gate-induced drain leakage current is proposed by using the drain-induced energy-barrier reduction in our model. The calculated results using the developed quasi-2-D model are in good agreement with measured values for a wide range of gate and drain biases. Therefore, the proposed new model can be used to simulate the hot-carrier band-to-band tunneling current for p-channel flash memory device.

Microwave electronics device applications of AlGaN/GaN heterostructures

One thrust in the recent AlGaN/GaN based HFET development hinges on the use of SiC substrates for the growth of the AlGaN/GaN heterostructures. We have achieved G m and maximum drain current ( I max) as high as 222 mS mm −1 and 1.71 A mm −1 for HFETs grown on n-SiC. The HFETs on p-SiC have also shown G m and I max of 230 mS mm −1 and 1.43 A mm −1. These devices exhibited cut-off frequency ( f t) and frequency of oscillation ( f max) of 55 and 56 GHz for HFETs on p-SiC, further demonstrating the applicability of AlGaN/GaN-based HFETs in high power microwave frequency range. The availability of high quality AlGaN/GaN heterostructure has also permitted the implementation of such new device concept as metal–insulator–semiconductor FETs (MISFETs). Our MISFETs have shown low gate leakage in ±6 V gate bias range with G m as high as 86 mS mm −1.

Sub-micron strained Si:SiGe heterostructure MOSFETs

Si:SiGe heteroepitaxy raises the prospect of combining the attributes of high mobility channel engineering with mainstream stricon MOS technology. The design of the heteroepitaxial structure is investigated here by means of a response surface methodology study of strained SiGe p-channel heterostructure MOSFETs using two-dimensional numerical device simulation. The reduced effective density of states inherent in a strained channel layer is included and shown to result in a lower inversion charge concentration in the channel. Particular performance metrics evaluated are the gate bias range for buried channel operation and the maximum channel charge, which determines the peak transconductance ( g m) and maximum current drive. It is shown that at the high levels of sub-channel doping appropriate for MOSFETs with sub-micron channel lengths, a small or non-existent window of buried channel operation may arise due to the onset of parasitic surface inversion. Various means of increasing the contribution of strained channel conduction to the drain current are considered, including composition grading and modulation doping. The conclusions are equally applicable to strained silicon n-channel heterostructure MOSFETs.

4H-SiC MESFET with 65.7% power added efficiency at 850 MHz

4H-SiC MESFET's on conducting substrates were fabricated and characterized for large-signal performance over a wide range of gate and drain biases. At V/sub ds/=25 V the current density was 225 mA/mm and the peak f/sub max/ for these devices was 16 GHz. At V/sub ds/=50 V and I/sub dq/=50% I/sub dss/, the power density was 3.3 W/mm at 850 MHz. At V/sub ds/=40 V and I/sub dq/=5% I/sub dss/, the power added efficiency was 65.7%, which is the highest ever reported for a SiC MESFET. This is the first Class B data presented for a SiC MESFET.

A new charge conserving capacitance model for GaAs MESFET's

We present a new charge conserving capacitance model for Gallium-Arsenide (GaAs) metal semiconductor field effect transistors (MESFET's) based on the quasi-static approximation and a proper partitioning of the channel charge between the source and the drain terminals. A total of nine so-called transcapacitances were determined by taking derivatives of the various terminal charges with respect to the voltages at source, drain, and gate. The transcapacitances are nonreciprocal, i.e., C/sub ij//spl ne/C/sub ji/ when i/spl ne/j, and can be organized in a 3/spl times/3 matrix incorporating Kirchhoff's current law (charge conservation) and independence of reference. The present capacitance model is valid both above and below threshold, and shows good agreement with experimental data over a wide range of gate and drain biases. The model is analytical and suitable for implementation in circuit simulators.

An analytical model for the above-threshold characteristics of polysilicon thin-film transistors

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E/sub c/-0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Temperature activated conductance in GaN/AlGaN heterostructure field effect transistors operating at temperatures up to 300 °C

We report on the dc characteristics and microwave performance of AlGaN/GaN heterostructure field effect transistors in the temperature range from 25 to 300 °C. At temperatures above 200 °C, we observe the temperature activated shunt conductance which is independent of the gate voltage (the activation energy is 0.505 eV). The cutoff frequency and the maximum frequency of oscillations vary from 22 and 70 GHz at 25 °C to 5 and 4 GHz at 300 °C, respectively. The gate leakage current in the range of gate biases from −4 to +1 V is small and nearly proportional to the gate voltage even at 300 °C. At temperatures above 200 °C, the gate leakage current is temperature activated (the activation energy is 0.88 eV). These results show that deep traps strongly affect the AlGaN/GaN characteristics at elevated temperatures.

A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85- mu m) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V/sub d//8 to V/sub d/) by hot-hole and/or hot-electron injections, and their generation rates (10/sup -9/ and 10/sup -2/ for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I/sub d/-V/sub g/ degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I/sub d/-V/sub g/ degradation. >

An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates

A simple closed-form expression of the threshold voltage is developed for trench-isolated MOS (TIMOS) devices with feature size down to the deep-submicrometer range. The analytical expression is the first developed to include the nonuniform doping effect of a narrow-gate-width device. The inverse narrow width effect can be predicted analytically from the proposed model. It was derived by modeling the gate sidewall capacitance to include the two-dimensional field-induced edge fringing effect and solving the Poisson equation to include the channel implant effect at different operating backgate biases. A two-dimensional simulation program was developed, and the simulated data were used for verification of the analytical model. Good agreements between the modeled and simulated data have been achieved for a wide range of gate widths and biases. The model is well suited for the design of the basic transistor cell in DRAM circuits using trench field oxide isolation structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Circuit performance of CMOS technologies with silicon dioxide and reoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO/sub 2/) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V/sub GS/<or=5 V and B/sub DS/<or=5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO/sub 2/ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower mu /sub p/ (hole mobility) of RONO p-channel devices. At 300 K, mu /sub p/(RONO) is 14-8% smaller than mu /sub p/(SiO/sub 2/) over the entire range of gate biases, while mu /sub n/(RONO) (electron mobility of n-channel RONO devices) is also smaller than mu /sub n/(SiO/sub 2/) and reaches only 96% of mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V. At 100 K, mu /sub n/(RONO)/ mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V is increased to 1.10, however, mu /sub p/(RONO)/ mu /sub p/(SiO/sub 2/) at V/sub GS/=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO/sub 2/ inverters.<<ETX>>

Monte Carlo simulation of 0.35- mu m gate-length GaAs and InGaAs HEMTs

A first-principles theoretical comparison of the performances of identical Al/sub 0.32/Ga/sub 0.68/As/GaAs and Al/sub 0.15/Ga/sub 0.15/As/In/sub 0.15/Ga/sub 0.85/As/GaAs pseudomorphic HEMTs based on an ensemble Monte Carlo simulation coupled with a two-dimensional Poisson solver is presented. The Monte Carlo calculations incorporate the full physics of the device operation. As a test of the accuracy with which the calculations successfully model a real device, the calculated current-voltage characteristic of the pseudomorphic device is first compared to recent experimental measurements made on a comparable structure, showing excellent agreement over a full range of gate and drain biases. The device performance as measured in terms of the transconductance, cutoff frequency, and current-voltage characteristics of both devices can then be compared as a function of gate and drain bias. It is found that the pseudomorphic HEMT outperforms the conventional GaAs/AlGaAs device by approximately a factor of two in the above-mentioned criteria. The greatly improved performance of the pseudomorphic HEMT over the GaAs device stems predominantly from greater confinement of the electrons within the high-mobility two-dimensional system, higher electron drift velocity, and greater gamma valley confinement. >

Kink-free AlInAs/GaInAs/InP HEMTs grown by molecular beam epitaxy

Kink-free AlInAs/GaInAs/InP HEMTs have been fabricated from an MBE structure grown under normal growth condition. Devices with 1 μm gate-length exhibit an extrinsic transconductance of 450mS/mm and a maximum drain current of 600mA/mm which represent the best results for 1 μm gate devices. The DC output conductance shows no kink over the entire gate bias range. The elimination of the kink is attributed to the high quality AlInAs buffer layer and a low mismatch between the AlInAs buffer layer and InP substrate.

Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process

The practical applications and limitations of four methods for extracting the effective channel length (L/sub eff/) and series resistance (R/sub ext/) parameters for MOS devices are studied. The methods are: GD (gate drive) using fixed-current V/sub t/ or GD(I/sub ds/); SBGD (substrate-bias GD) using fixed-current V/sub t/ or SBGD (I/sub ds/); GD using maximum slope V/sub t/ or GD (G/sub m/); and SBGD using maximum slope V/sub t/ or SBGD (G/sub m/). Conventional and two LDD (lightly doped drain) structures fabricated in a submicrometer CMOS process are used. The results indicate that all the extraction methods are applicable to both n-channel and p-channel devices, although some are only valid over a small range of gate biases. Inconsistencies in applying V/sub t/ calculations to the extraction equations set a lower limit for V/sub gst/ of approximately 0.5 V, while the upper limit of 2.0-4.0 V arises due to imprecision in R/sub ds/ measurements influencing the double regression steps involved in the techniques. The SBGD (I/sub ds/) method was applicable over a wider range of bias conditions than the other techniques analyzed and is easier to implement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ensemble Monte Carlo simulation of a 0.35- mu m pseudomorphic HEMT

Theoretical analysis and precise comparison to experiment of the performance of a 0.35- mu m pseudomorphic Al/sub 0.15/Ga/sub 0.85/As/In/sub 0.15/Ga/sub 0.85/As high-electron-mobility transistor (HEMT) are presented. The calculations are made using an ensemble Monte Carlo simulation with the unique inclusion of real space transfer as well as the full details of the two-dimensional electron gas, velocity overshoot, and ballistic transport, and the effects of the two-dimensional electric field profile. The calculated current-voltage characteristic is compared to recent experimental measurements showing excellent agreement to within approximately 10% over a full range of gate and drain biases. It is found that near the source, the two-dimensional system dominates the transport physics, while near the pinch-off point, the effects of real space transfer become apparent. It is further determined that the high-speed performance of the pseudomorphic HEMT stems predominantly from the high electron confinement within the two-dimensional system, and the high electron mobility and confinement within the gamma valley in the bulk InGaAs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Estimating and Reducing Errors in MOS Dosimeters Caused by Exposure to Different Radiations

This paper is concerned with the errors that can result because of charge recombination differences in the SiO2 layer of a PMOS transistor that is to be employed as an integrating dosimeter aboard an earth-orbiting satellite. The space radiation environment consists mostly of electrons and protons of various energies. These electrons and protons will produce tracks with different ionization densities in the SiO2. Consequently there will be differences in the amount of charge recombination, and these differences will be reflected as errors in the dose measurements. Data have been obtained on the devices for different radiations. Saturation curves relating the shift in threshold voltage, ?VT, per krad (SiO2) as a function of gate bias during irradiation, VG, are obtained for devices exposed to Co-60 gamma rays, electrons with a most probable energy of 7 MeV, 37-MeV protons, and Cu X rays. A renormalization procedure is applied to the saturation curves in order to remove from consideration the confusing effects caused by systematic errors in the dosimetry. The resulting set of curves then permit the determination of the errors in dose measurement associated with only charge recombination. From these data the allowable range of gate bias is determined that will result in reasonably accurate measurements of dose in the space radiation environment. For a given choice of gate bias, the set of renormalized curves also yields an objective estimate of the possible error associated with differences in charge recombination.

Measurement of MOSFET constants

A method is described to electrically determine MOSFET channel length, mobility, gate-bias dependence and parasitic series resistance. These four quantities are obtained by curve fitting output resistance measurements over a range of gate biases and channel lengths. Measurements from two gate biases on each of two devices of different channel lengths are sufficient to obtain a full characterization. Thus, the method is well suited for automated testing because of its simplicity and efficiency.

Radiation Effects on MOS Power Transistors

The use of power MOS transistors in spacecraft and military equipment is limited by their vulner-ability to ionizing radiation (total-dose and doserate). The total-dose hardness of four types of power MOS is examined in this paper. All devices experience comparable shifts of VGS(th) following total-dose exposure. Other functional parameters are not affected by dose up to half a megarad. Thus, an effective hardening technique consists of extending the range of gate bias and gate drive to allow operation at high dose levels. The results of dose-rate testing of three types of power MOS are presented and analyzed. Photocurrent burnouts are tentatively attributed to thermally induced second breakdown of the drain-source diode. Decreasing the carrier lifetime of the junction material is anticipated to decrease this vulnerability.

Stress-sensitive properties of silicon-gate MOS devices

Stress-sensitive properties were measured on both p- and n-channel silicongate MOS devices fabricated on (100) Si at room temperature. Stress-induced variations in drain currents for both enhancement- and depletion-mode MOS transistors with various channel-dopings were measured over a wide range of gate biases. In addition to piezoresistance effect, remarkable drain-current variations were observed at weak-inversion and explained theoretically in terms of changes in minority carrier densities due to energy band shifts by stresses. Elastoresistance shear-constants for polycrystalline-silicon gate layers were also obtained and compared with coefficients for source-drain diffused layers. Further, the elastoresistance of p-type polycrystalline-silicon films was investigated on doping-concentration dependences. A theoretical model for polycrystalline-silicon elastoresistance was developed based on the barrier model for conductivity in polycrystalline-silicon. Results obtained from the model were compared with the experimental results and found to be in good agreement at higher doping-concentrations than trap density.

Radiation Hardening of P-MOS Devices by Optimization of the Thermal Si02 Gate Insulator

It has been found for p-channel MOS devices that considerably better radiation tolerance than generally believed possible can be obtained with gate insulators of thermally grown SiO2, provided that the processing conditions are optimized for radiation resistance. The oxidation ambient and temperature, the post-oxidation annealing temperature, the silicon orientation, and the method of depositing the gate metal all have pronounced effects on the radiation-induced degradation. With these parameters optimized for radiation hardness, gate threshold shifts of less than one volt after 1 × 106 rads (Si) can be obtained over the entire range of gate biases from 0 to -30 volts. This paper describes these findings and their applicability to the fabrication of radiation-hardened MOS circuits.

Carrier mobility in silicon MOST's

The mobility and density of free carriers in surface channels have been obtained from conductivity and Hall measurements performed on large experimental silicon MOST's. Uniform n- and p-type channels, with various crystallographic orientations have been studied over a range of temperatures, gate biases, and reverse biases between the channel and substrate. No trapping of induced carriers has been observed when the gate voltage is more than a few volts above threshold. The mobility of free carriers is very small at threshold. It increases rapidly with gate voltage and shows a maximum of about 1 3 or 1 2 of its bulk value, at gate voltages corresponding to free carrier densities of about 2–7 × 10 11 carriers/cm 2. At larger gate voltages the mobility shows a slow decrease. The mobility is also affected by bias between channel and substrate. A hysteresis in channel conductance is observed at room temperature. It is shown that a hysteresis in carrier mobility contributes appreciably to this effect. Finally, it is demonstrated by means of an example that the variations of mobility with gate and substrate bias have an appreciable influence on the drain characteristics of MOST's.