Gate Bias Range Research Articles

Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy

Due to the fact that either holes or electrons can band-to-band-tunnel (BTBT) through channelsource/drain contacts, tunneling carbon nanotube field effect transistors (T-CNFETs) suffer from ambipolar transporting characteristic. To suppress such ambipolar conductance, a novel device design based on stair-case doping strategy of drain region is proposed first in this paper. The dependences of available ON-OFF current ratio, practical ON-OFF current ratio with certain gate bias range and the average sub-threshold swing on the doping level of drain region are studied. Simulation results show that such device design can not only increase the ON-OFF current ratio largely but also result in a clear decrease of sub-threshold swing. At the same time, however, such stair-case doping strategy would broaden the depletion region and result in an increase of device area cost. Particular attention should be paid to the choice of doping level of drain region to make a proper tradeoff between power, speed and area in application.

Self-consistent 1-D Schrödinger–Poisson solver for III–V heterostructures accounting for conduction band non-parabolicity

We present in this paper a novel method to solve self-consistently the Schrödinger and Poisson’s equations with non-parabolic conduction bands in III–V heterostructures with one dimensional material and electrostatic potential variation. Our calculation suggests ∼20% more sheet charge density ( N s ) may be expected for a representative quantum well FET structure featuring an InGaAs channel cladded with an AlGaSb barrier, compared to predictions from the parabolic band assumption; N s reaches >5 × 10 12 cm −2 at 0.8 V gate overdrive. The increase in sheet density directly results in a higher FET gate capacitance and therefore better transconductance, which stems from the different density of states (DOS) function with the non-parabolic conduction band. Calculation demonstrates that non-parabolicity results in a “tilted staircase” DOS function (as opposed to the classical “flat staircase”). This model was also extended to accommodate satellite valleys, which allows the proper FET gate bias range to be determined in order to avoid overall carrier mobility drop due to L-valley occupation.

Stress test measurements of lattice‐matched InAlN/AlN/GaN HFET structures

AbstractInAlN/GaN heterostructures offer some benefits over existing AlGaN/GaN heterostructures for HFET device applications. In addition to having a larger bandgap than typical AlGaN compounds used in HFET devices (with Al < 30%), which leads to better confinement and subsequent larger power carrying capacity, InAlN can be grown lattice‐matched to GaN, resulting in strain‐free heterostructures. As such, lattice‐matched InAlN provides a unique system wherein the reliability of the devices may exceed that of the strained AlGaN/GaN devices as a result of being able to decouple the hot electron/hot phonon effects on the reliability from the strain related issues. In this work, we subjected lattice‐matched InAlN‐based HFETs to electrical stress and observed the corresponding degradation in maximum drain current. We found that the degradation rates are lower only for a narrow range of moderate gate biases, corresponding to low field average 2‐dimensional electron gas (2DEG) densities of 9–10 × 1012 cm−2. We propose that the degradation is attributable to the buildup of hot phonons since the degradation rates as a function of electron density generally follow the hot phonon lifetime versus electron density. This provides evidence that hot phonons have a significant role in device degradation and there exists an optimal 2DEG density to minimize hot phonon related degradation. We did not observe any correlation between the degradation rate and the gate leakage.

Physical Modeling for Programming of TANOS Memories in the Fowler–Nordheim Regime

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.

Zero-field spin splitting and spin-dependent broadening in high-mobilityInSb/In1−xAlxSbasymmetric quantum well heterostructures

We present high field magneto-transport data from a range of 30nm wide InSb/InAlSb quantum wells. The low temperature carrier mobility of the samples studied ranged from 18.4 to 39.5 m2V-1s-1 with carrier densities between 1.5x1015 and 3.28x1015 m-2. Room temperature mobilities are reported in excess of 6 m2V-1s-1. It is found that the Landau level broadening decreases with carrier density and beating patterns are observed in the magnetoresistance with non-zero node amplitudes in samples with the narrowest broadening despite the presence of a large g-factor. The beating is attributed to Rashba splitting phenomenon and Rashba coupling parameters are extracted from the difference in spin populations for a range of samples and gate biases. The influence of Landau level broadening and spin-dependent scattering rates on the observation of beating in the Shubnikov-de Haas oscillations is investigated by simulations of the magnetoconductance. Data with non-zero beat node amplitudes are accompanied by asymmetric peaks in the Fourier transform, which are successfully reproduced by introducing a spin-dependent broadening in the simulations. It is found that the low-energy (majority) spin up state suffers more scattering than the high-energy (minority) spin down state and that the absence of beating patterns in the majority of (lower density) samples can be attributed to the same effect when the magnitude of the level broadening is large.

Gated tunnel diode in oscillator applications with high frequency tuning

A gated tunnel diode has been introduced into a wave-guide oscillator circuit and the gate is used to tune the oscillation frequency and to turn the oscillator on and off. Oscillators with oscillation frequencies in the range of 9–22 GHz with a typical oscillator output power about −20 dBm have been fabricated. We found that the output power remains essentially constant over a gate bias range (about −260–200 mV at V c = 1.0 V in one oscillator), while it rapidly drops to the noise level over a gate bias range of less than 60 mV above or below the threshold, respectively. In the region with constant power, a total frequency tuning of about 30% is achieved. The maximum oscillation frequency, f max osc , of the gated tunnel diode is set by the tunnel diode and the gate–collector capacitance, and does not depend on the gate–emitter capacitance. This oscillator implementation, in particular, eliminates the need for a separate switch in the realisation of oscillator-based ultra-wide band impulse radios.

Low frequency noise in 4H-SiC metal oxide semiconductor field effect transistors

The low frequency noise was studied in 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) in the frequency range from 1 Hz to 100 kHz. 1/f (flicker) noise dominated in output noise over the entire frequency range and for a wide range of drain and gate biases. The dependence of the relative spectral noise density, SI/Id2, on the drain current, Id (at constant drain voltage, Vd), was qualitatively different from typical dependences for n-channel Si MOSFETs. In Si MOSFETs, in strong inversion, SI/Id2 usually decreases as ∼1/Id2 and tends to saturate in the subthreshold region, whereas in SiC MOSFETs under study, SI/Id2∝Id−0.5 for the currents varying from the deep subthreshold regime to the strong inversion. [Similar dependences were often observed in amorphous and polycrystalline thin film transistors (TFTs).] The effective field effect mobility of 3–7 cm2/V s extracted from the measured I-V characteristics is almost as low as that in amorphous Si TFTs. This result might be explained by a high density of localized states near the conduction band in the thin ion implanted silicon carbide layer. The energy dependence of trap density responsible for the noise was extracted for the states located close to the bottom of conduction band.

전력 증폭기의 Behavioral 모델링을 위한 E-TDLNN 방식에 관한 연구

In this paper, E-TDLNN(Expanded-Tapped Delay Line Neural Network) method is suggested to make the model of power amplifier effectively. This method is the one for making the model of power amplifier through the study in neural network to the target value, the measured output spectrum of power amplifier, after adding the external value factor, gate bias, as an invariant input to the TDLNN method which suggested the memory effect of power amplifier effectively. To prove the validity of suggested method, the data at 2 points, 3.45 V and 3.50 V of gate bias range with the 0.01 V step change, are studied and the predicted results at the gate bias 3.40 V, 3.48 V, 3.53 V and 3.60 V shows good coincidence with the measured values.

Coulomb attractive random telegraph signal in a single-walled carbon nanotube

The gate dependence of a Coulomb attractive random telegraph signal is observed in a single-walled carbon nanotube field effect transistor for temperatures varying from 0.32 to $24\phantom{\rule{0.3em}{0ex}}\mathrm{K}$. The mechanism of the Coulomb attractive random telegraph signal is attributed to the carrier tunneling between the carbon nanotube and the Coulomb attractive defect. The random telegraph signal is also studied under magnetic field over an entire gate bias range and a wide temperature range. The Coulomb attractive random telegraph signal shows weak magnetic dependence, which may be due to the broadening of the Zeeman levels of the defect in the $p$-type carbon nanotube field effect transistor.

Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region

Novel metal-oxide-semiconductor (MOS)-based single-electron transistors (MOSETs) using band-to-band tunneling mechanism have been fabricated by the conventional silicon-on-insulator (SOI) MOSFET technologies. The fabricated SETs have tunnel barriers and quantum-dot formed by an extremely small channel between two p+-n+ tunnel junctions in the degenerately doped SOI MOSFET. Coulomb oscillation was observed in the subthreshold region at liquid nitrogen temperature and total capacitance of quantum-dot is 2.25 aF which is well matched to the device geometry. In order to validate the operation principle of our device, we have implemented an analytical device model in the simulation program with integrated circuit emphasis (SPICE). SPICE simulation of our model with a unique distribution function has reproduced the experimental results with good agreement for wide gate and drain bias range.

On-die termination resistors with analog impedance control for standard CMOS technology

In this paper, we have designed a new voltage-controlled resistor for the purpose of on-die termination in standard CMOS technology. Current-voltage (I-V) characteristics show that this on-die termination resistor has good linearity across a wide range of gate bias, and is suitable for an analog impedance control technique using a feedback loop. The analog impedance control technique has the advantage of continuous impedance adjustment without interfering with normal data transmission and receiving operations. Experimental I-V characteristics show excellent linearity and are in good agreement with simulations. Measured resistance values are within /spl plusmn/5% over process, temperature, and across die variations.

Analysis of Narrow Width Effects in Polycrystalline Silicon Thin Film Transistors

In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.

An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET

An analytic three-terminal band-to-band tunneling current model for the gate-induced drain leakage current (GIDL) in an n-MOSFET is developed. This model considers impurity doping concentration, vertical field, lateral field, and so-induced electron momentum enhancement, as well as the surface electro-static potential in the gate-to-drain overlapped region. Based on a constant surface-potential approximation, a closed-form equation has been obtained instead of the complex integral-form in previous works. The results from this new model show good agreement with the measurement data over a wide range of gate and drain biases and device channel lengths. This work is useful for GIDL analysis in transistor design as well as in circuit simulation.

An empirical model for leakage current in poly-silicon thin film transistor

The electric fields present in drain depletion region of poly-silicon thin film transistors (poly-Si TFTs) result in the enhancement of emission rate from the traps. An empirical relation between the field enhanced emission rate and electric field is proposed, which can be used to model the leakage current of poly-Si TFTs as a function of gate bias and temperature. The leakage current shows good agreement with the experimental data over wide range of temperature and gate bias. The model can be useful for circuit simulation.

Low-frequency noise in cadmium-selenide thin-film transistors

Low-frequency noise in cadmium-selenide (CdSe) thin-film transistors (TFTs) has been studied over a wide range of gate and drain biases, temperatures, and gate areas. The dependencies of the noise on the gate voltage and the gate length indicate that the 1/f noise originates from the bulk sources homogeneously distributed in the channel. The value of Hooge parameter α lies within the usual range 10−3<α<2×10−2 for Si TFTs and amorphous Si.

A novel channel resistance ratio method for effective channel length and series resistance extraction in MOSFETs

A resistance ratio method for electrical effective channel length and series resistance extraction is developed and verified on an advanced 0.35 μm LDD CMOS technology. This method avoids the gate bias range optimization required in the widely used “shift-and-ratio” (S&R) method, which is usually technology specific, while retaining the single transistor algorithm nature of S&R.

Scattering mechanisms limiting two-dimensional electron gas mobility in Al0.25Ga0.75N/GaN modulation-doped field-effect transistors

In order to characterize the electron transport properties of the two-dimensional electron gas (2DEG) in AlGaN/GaN modulation-doped field-effect transistors, channel magnetoresistance has been measured in the magnetic field range of 0–12 T, the temperature range of 25–300 K, and gate bias range of +0.5 to −2.0 V. By assuming that the 2DEG provides the dominant contribution to the total conductivity, a one-carrier fitting procedure has been applied to extract the electron mobility and carrier sheet density at each particular value of temperature and gate bias. Consequently, the electron mobility versus 2DEG sheet density has been obtained for each measurement temperature. Theoretical analysis of these results suggests that for 2DEG densities below 7×1012 cm−2, the electron mobility in these devices is limited by interface charge, whereas for densities above this level, electron mobility is dominated by scattering associated with the AlGaN/GaN interface roughness.

A channel resistance derivative method for effective channel length extraction in LDD MOSFETs

A channel resistance derivative method for extracting the electrical effective channel length and series resistance is proposed, and demonstrated on an advanced 0.35 /spl mu/m LDD CMOS technology. A clear graphic image of the L/sub EFF/ and R/sub SD/ is obtained directly from the measured channel resistance and its derivative with respect to the gate bias. The method also provides guidelines for the proper gate bias range selection in traditional L/sub EFF/ extraction techniques.

Microwave power performance comparison between single and dual doped-channel design in AlGaAs/InGaAs HFETs

Single and dual doped-channel AlGaAs/InGaAs FETs (DCFETs) were fabricated, characterized, and compared with each other in terms of dc, rf, and power performance. The dual doped channel design provides a higher current density, and a better linear operation range over a wide gate bias range and frequency. A 1 μm-long gate dual-DCFET operated at 1.9 GHz demonstrates a power-added efficiency of 51.5%, a gain of 19 dB, and an output power density of 305 mW/mm at 2.5 V. This performance suggests that dual doped-channel design is more suitable for linear and high power microwave device applications.

Localization effect in mesoscopic quantum dots and quantum-dot arrays

We discuss the observation of an unusual type of localization in split-gate quantum dots and quantum-dot arrays. While no evidence for its existence is found prior to biasing the gates, the localization persists to conductance values as high as $50{e}^{2}/h$ and is not destroyed by the application of a weak magnetic field. The carrier density in the dots remains constant over the range of gate bias studied and these characteristics suggest that the localization is quite distinct to that studied previously in two-dimensional semiconductors. We suggest that a confinement-induced enhancement of the electron-electron interaction may be responsible for the localization and propose a simple functional form which allows us to account for its variation as a function of either temperature or source-drain voltage.