Sub-micron strained Si:SiGe heterostructure MOSFETs

Abstract

Si:SiGe heteroepitaxy raises the prospect of combining the attributes of high mobility channel engineering with mainstream stricon MOS technology. The design of the heteroepitaxial structure is investigated here by means of a response surface methodology study of strained SiGe p-channel heterostructure MOSFETs using two-dimensional numerical device simulation. The reduced effective density of states inherent in a strained channel layer is included and shown to result in a lower inversion charge concentration in the channel. Particular performance metrics evaluated are the gate bias range for buried channel operation and the maximum channel charge, which determines the peak transconductance ( g m) and maximum current drive. It is shown that at the high levels of sub-channel doping appropriate for MOSFETs with sub-micron channel lengths, a small or non-existent window of buried channel operation may arise due to the onset of parasitic surface inversion. Various means of increasing the contribution of strained channel conduction to the drain current are considered, including composition grading and modulation doping. The conclusions are equally applicable to strained silicon n-channel heterostructure MOSFETs.