Abstract
Device modeling, device design optimization for specific applications, and future trends in power MOSFET technology are examined. A DMOS FET technology with 2.5 million cells/inch/sup 2/ and submicron channel length that minimizes on-resistance is introduced. By implementing an optimized gate oxide and a submicron channel length, specific-on-resistances of 1.3 to 1.4 m Omega -cm/sup 2/ for a 50 V DMOS FET and 1.5 to 1.65 m Omega -cm/sup 2/ for a 60 V DMOS FET have been achieved. This technology yields low specific on-resistance and ruggedness simultaneously. As shown, a 60 V, 18 m Omega rated part in a TO-220 package sustains 202 A under UIS testing. The 2.5 million cells/inch/sup 2/ DMOS FET technology not only has 40-50% smaller die size, but also lower gate charge for the same on-resistance. The basic process architecture allows the flexibility to fabricate a 30 V DMOS FET with less than 0.9 m Omega -cm/sup 2/ by changing the starting process with low resistivity silicon. These low on-resistances have been achieved in high-volume manufacturing. >
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