Gate Bias Range Research Articles

높은 전자이동도를 가지는 산화인듐 박막트랜지스터의 제조 및 특성분석

We report fabrication of high-mobility In2O3 thin-film transistors (TFTs) and their characterization. In2O3 thin film was deposited by radio-frequency magnetron sputtering method and used as a channel layer. Electrical characterizations revealed excellent performance of the fabricated TFTs such as high ON current, large Imax/Imin ratio, and formation of good Ohmic junctions. Uniform transconductance was observed over large range of gate bias. Especially, transmission line method was applied for different gate overdrive bias Values to extract the effective gate lengths of the fabricated TFTs. This analysis enables to accurately derive the field effect mobility of the TFTs, where the maximum value was calculated to be 53.8 cm2/Vs.

Ultra-low power neuromorphic obstacle detection using a two-dimensional materials-based subthreshold transistor

Accurate, timely and selective detection of moving obstacles is crucial for reliable collision avoidance in autonomous robots. The area- and energy-inefficiency of CMOS-based spiking neurons for obstacle detection can be addressed through the reconfigurable, tunable and low-power operation capabilities of emerging two-dimensional (2D) materials-based devices. We present an ultra-low power spiking neuron built using an electrostatically tuned dual-gate transistor with an ultra-thin and generic 2D material channel. The 2D subthreshold transistor (2D-ST) is carefully designed to operate under low-current subthreshold regime. Carrier transport has been modeled via over-the-barrier thermionic and Fowler–Nordheim contact barrier tunneling currents over a wide range of gate and drain biases. Simulation of a neuron circuit designed using the 2D-ST with 45 nm CMOS technology components shows high energy efficiency of ~3.5 pJ per spike and biomimetic class-I as well as oscillatory spiking. It also demonstrates complex neuronal behaviors such as spike-frequency adaptation and post-inhibitory rebound that are crucial for dynamic visual systems. Lobula giant movement detector (LGMD) is a collision-detecting biological neuron found in locusts. Our neuron circuit can generate LGMD-like spiking behavior and detect obstacles at an energy cost of <100 pJ. Further, it can be reconfigured to distinguish between looming and receding objects with high selectivity. We also show that the spiking neuron circuit can function reliably with ±40% variation in the 2D-ST current as well as up to 3 dB signal-to-noise ratio with additive white Gaussian noise in the input synaptic current.

Persistent charge storage and memory operation of top-gate transistors solely based on two-dimensional molybdenum disulfide

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths.

A New Charge-Based Analytical Model for the Gate Current in GaN HEMTs

In this article, we present a new charge-based analytical model for the gate current in GaN HEMTs, using an existing model, and modifying it by including the effect of the barrier layer charge, as well as the potentials dropped across the gate–source and gate–drain access regions. Individual models have been presented for the four contributors to the gate current, namely Poole–Frenkel emission (PFE), Fowler–Nordheim tunneling (FNT), thermionic emission (TE), and defect-assisted tunneling (DAT). We have also proposed a new analytical expression for the parameter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{0}}$ </tex-math></inline-formula> , appearing in the model for the DAT current. The model results have been compared with the experimental data reported in the literature for both AlGaN/GaN and AlInN/GaN HEMTs over a wide range of gate bias and temperature, and for both zero and nonzero drain–source bias, with the match being found to be excellent, thus validating our model.

Over 1200 V Normally-OFF p-NiO Gated AlGaN/GaN HEMTs on Si With a Small Threshold Voltage Shift

In this letter, we demonstrated a normally-off AlGaN/GaN HEMT using p-NiO as a gate stack combined with a recess structure. The fabricated HEMT exhibits a positive threshold voltage of 1.73 V, a saturation output current of 524 mA/mm, a small subthreshold swing of 79.7 mV/dec and a maximum transconductance as high as 143 mS/mm. This is the first time to demonstrate the breakdown characteristics of a p-NiO gate HEMT with a high breakdown voltage of 1205 V and a low specific ON-resistance of 2.22 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula>cm², yielding a competitive Baliga&#x2019;s figure-of-merit of 0.65 GW/cm². The instability evaluation of <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> by step stress and pulse transfer curves shows that the p-NiO gate HEMT has a negligible <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift in the entire measured gate bias range, which can be attributed to the counteraction between the electron trapping-induced positive <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {TH}}$ </tex-math></inline-formula> shift and hole accumulation induced-negative <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. It is well understood in terms of the carrier transport model based on the large band discontinuity at the interface of the p-NiO/AlGaN type-II heterojunction, which is further verified by transient gate current spectra.

Composite‐channel In 0. 17 Al 0 . 83 N /In 0. 1 Ga 0 . 9 N / GaN /Al 0. 04 Ga 0 . 96 N high electron mobility transistors for RF applications

In this work, we present the high performance of composite channel based In0.17Al0.83N/In0.1Ga0.9N/GaN/Al0.04Ga0.96N high electron mobility transistors (HEMTs) on a sapphire substrate. A numerical simulation is carried out for the proposed and conventional GaN channel-based HEMTs using TCAD. Due to the strong polarization of InAlN/InGaN, enhanced electron confinement and high electron mobility of composite channel based proposed device shows excellent DC and RF characteristics with improved linearity than conventional GaN channel based HEMTs. A 55 nm T-gate device demonstrates 4.45 A/mm drain current density (IDS) at VGS = 0 V, 0.7 S/mm stable transconductance (GM) for a wide range of gate bias, and excellent FT/Fmax of 274/288 GHz. Benefiting from the Al0.04Ga0.96N buffer (back-barrier), the device shows a very low sub-threshold drain leakage current and high breakdown voltage (VBR) of 43.5 V. The combination of high FT/Fmax, stable transconductance, and high breakdown voltage of the proposed HEMTs shows the great promise for high power and wide-bandwidth millimeter-wave applications.

Gate Current Transport in Enhancement-Mode p-n Junction/AlGaN/GaN (PNJ) HEMT

In this work, we study the gate leakage mechanisms of E-mode p- n junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the p-GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures.

Gate Current Partitioning Model for Schottky Gate GaN HEMTs

A gate current partition scheme for Schottky gate GaN-based high-electron-mobility transistors (HEMTs) using a charge-based approach is proposed. Analytical expressions for gate-to-drain and gate-to-source components of Fowler-Nordheim tunneling (FNT), Poole-Frenkel emission (PFE), thermionic emission (TE), and defect assisted tunneling (DAT) currents are derived. This current partition model is implemented in Verilog-A and validated with experimental results for a wide range of gate and drain bias. The model also passes the symmetry test.

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

Due to the ultra-thin nature and moderate carrier mobility, semiconducting two-dimensional (2D) materials have attracted extensive attention for next-generation electronics. However, the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications. Herein, the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully. The transistor performance is found to be strongly affected by the gate bias stress time, sweeping rate and range, and temperature. Based on the systematical study and complementary analysis, charge trapping is determined to be the major contribution for these observed phenomena. Importantly, due to these charge trapping effects, the channel current is observed to decrease with time; hence, a rate equation, considering the charge trapping and time decay effect of current, is proposed and developed to model the phenomena with excellent consistency with experimental data. All these results do not only indicate the validity of the charge trapping model, but also confirm the hysteresis being indeed caused by charge trapping. Evidently, this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors, which can be also applicable to other kinds of transistors.

Rapid Four-Point Sweeping Method to Investigate Hysteresis of MoS2 FET

Hysteresis is a frequently observed phenomenon in the transfer characteristics of thin film transistors. Charge trapping/de-trapping processes of gate oxide and gate-channel interface are commonly known to be the origin of hysteresis and correlated to low frequency noise (LFN) properties of the devices. In this letter, a rapid four-point sweeping method (RFSM) is proposed to reveal the dependence of hysteresis, as well as the distribution of effective trap density on sweeping rate and gate bias range. Based on the RFSM, the hysteresis properties of four-layer MoS2 FETs are studied in detail. The experimental results demonstrate that the hysteresis and trap density at different frequencies and gate voltages, which could further roughly map the traps with different time constants and energy depths, can be obtained by the simple RFSM. Trap density estimated by RFSM shows a comparable range with that extracted from LFN, indicating that the traps inducing the hysteresis may also cause LFN.

A new approach to RF small-signal modeling of MOSFETs

In this paper, we present a new approach to obtain the RF small-signal parameters of MOSFETs, by developing region-wise (strong- and weak-inversion) physics-based small-signal models for the intrinsic part of the device, and eventually coupling them over the moderate inversion region through the use of an interpolation function. The basic premise of this approach is the fact that there is a large difference between the magnitudes of the depletion and inversion charge densities in strong- and weak-inversion regions. The expressions for the Y-parameters are obtained in a power series form, truncated up to the second-order, which is enough to retain sufficient accuracy. Since only the intrinsic parameters are not sufficient to predict the high frequency behavior of short-channel devices, hence, extrinsic parameters are coupled with their intrinsic counterparts in order to obtain the total values of the Y-parameters for the complete device. The results of our model show a sufficiently good match with the TCAD simulations. Also, the continuity of the various device capacitances at a frequency of 50 GHz over the entire range of gate bias validates our model.

Low optical turn-on voltage in solution processed hybrid light emitting transistor

Low optical turn-on voltage is realized in a solution processed hybrid light emitting transistor (LET). To achieve that, an original approach has been applied where an emissive polymer is mixed with a hole transport small molecule. While the high mobility solution processed oxide determines the main electrical characteristics of the transistor as the electron transport layer, the hole transport molecule acts as an immediate source of positive charges to the emissive polymer within its matrix, thus resulting in more efficient light emission when the transistor is turned-on electrically. While the electrical turn-on voltage remains almost the same, the light turn-on voltage significantly decreases from 27 V in the control device to 2 V in the blend device. Furthermore, brightness and external quantum efficiency are also considerably improved within the whole range of gate bias in the blend device, evidencing that our approach enhances overall optical performance of a solution processed hybrid LET.

Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified.

A flexible InGaAs nanomembrane PhotoFET with tunable responsivities in near- and short-wave IR region for lightweight imaging applications

An ultra-thin (15 nm) InGaAs nanomembrane field-effect phototransistor is transferred entirely from a rigid InP substrate onto a flexible SU-8 on a polydimethylsiloxane substrate. The transferred InGaAs device exhibits wide-band spectral response tunability up to 1.8 µm, from the visible to near-infrared light. Using an epitaxial lift-off process of InGaAs-on-InP MOSHEMT, the transferred device is inverted with a fully exposed channel for photosensitivity enhancement, while retaining three terminals for photocurrent amplification and modulation. The photocurrent can be tuned ∼5 orders over a gate bias range of 6 V. On-state photo-responsivities of 350 A/W to 15 A/W for 0.6 µm and 1.8 µm of light, respectively, is measured, ∼2 × higher than existing silicon and III-V photodetectors. Furthermore, the device shows no electrical performance degradation when flexed down to 10-cm radius, demonstrating suitability for conformal surface sensor applications.

Silicon Field Effect Transistor as the Nonlinear Detector for Terahertz Autocorellators.

We demonstrate that the rectifying field effect transistor, biased to the subthreshold regime, in a large signal regime exhibits a super-linear response to the incident terahertz (THz) power. This phenomenon can be exploited in a variety of experiments which exploit a nonlinear response, such as nonlinear autocorrelation measurements, for direct assessment of intrinsic response time using a pump-probe configuration or for indirect calibration of the oscillating voltage amplitude, which is delivered to the device. For these purposes, we employ a broadband bow-tie antenna coupled Si CMOS field-effect-transistor-based THz detector (TeraFET) in a nonlinear autocorrelation experiment performed with picoseconds-scale pulsed THz radiation. We have found that, in a wide range of gate bias (above the threshold voltage mV), the detected signal follows linearly to the emitted THz power. For gate bias below the threshold voltage (at 350 mV and below), the detected signal increases in a super-linear manner. A combination of these response regimes allows for performing nonlinear autocorrelation measurements with a single device and avoiding cryogenic cooling.

Gate leakage mechanisms in normally off p-GaN/AlGaN/GaN high electron mobility transistors

In this letter, gate leakage mechanisms in different gate contact normally off p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) have been studied by the temperature-dependent current-voltage (IG-VG) measurement. It is found that two-dimensional variable range hopping is responsible for gate leakage current at the reverse gate bias and low forward gate bias in both high-leakage and low-leakage Schottky gate contact devices. At high forward gate bias, in the case of high-leakage Schottky contact, the dominant current conduction mechanism is found to be thermionic field emission while it is Poole–Frenkle emission (PFE) for the case of low-leakage Schottky contact and the activation energy of trap states for PFE current is derived as 0.6 eV. Besides, related models are also proposed to describe the gate leakage current in p-GaN gate HEMTs and they match well with the experimental gate leakage current within a wide range of temperatures and gate biases.

Gate Leakage Mechanisms in AlInN/GaN and AlGaN/GaN MIS-HEMTs and Its Modeling

Gate leakage mechanisms in AlInN/GaN and AlGaN/GaN metal insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric have been investigated. It is found that the conduction in the reverse gate bias is due to Poole-Frenkel emission for both MIS-HEMTs. The dominant conduction mechanism in low to medium forward bias is trap-assisted tunneling while it is Fowler–Nordheim tunneling at high forward bias. However, conduction near zero gate bias is dominated by defect-assisted tunneling for both sets of MIS-HEMTs. The gate leakage current is primarily dependent on the properties of the gate dielectric material and dielectric/ semiconductor interface rather than the barrier layer. A model is proposed for the gate leakage current in GaN-based MIS-HEMTs, and the method to extract the related model parameters is also presented in this paper. The proposed gate current model matches well with the experimental results for both AlInN/GaN and AlGaN/GaN MIS-HEMTs over a wide range of gate bias and measurement temperature.

Electric Double Layer Dynamics in Poly(ethylene oxide) LiClO4 on Graphene Transistors

Formation of an electric double layer (EDL) is a powerful approach for exploring the electronic properties of two-dimensional (2D) materials because of the ultrahigh capacitance and induced charge in the 2D materials. In this work, epitaxial graphene Hall bar devices are gated with an EDL using a 1 μm thick solid polymer electrolyte, poly(ethylene oxide) and LiClO4. In addition to carrier density and mobility, ion dynamics associated with the formation and dissipation of the EDL are measured as a function of temperature over a gate bias range of ±2 V. The room temperature EDL formation time (∼1–100 s) is longer than the dissipation time (∼10 ms). The EDL dissipation is modeled by a stretched exponential decay, and the temperature-dependent dissipation times are described by the Vogel–Fulcher–Tammann equation, reflecting the coupling between polymer and ion mobility. At low temperatures, approaching the glass transition temperature of the electrolyte, the dissipation times of both cations and anions exceed...

Effect of thin gate dielectrics on DC, radio frequency and linearity characteristics of lattice‐matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor

In this paper, the authors present a polarisation dependent analytical model for DC, radio frequency (RF) and linearity characteristics of a proposed lattice-matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor (MOSHEMT). The developed model includes charge controlled analysis derived from triangular potential well approximation along with the spontaneous and piezoelectric polarisation effects. The model accurately predicts the threshold voltage, two-dimensional electron gas sheet charge density, drain current, transconductance and cut-off frequencies for different samples of gate dielectric materials such as SiO2, HfO2 and Al2O3 over a full range of gate and drain bias. A detailed analysis of the linearity characteristics by investigating the key figure-of-merit metrics such as second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion are performed for different gate dielectric thicknesses of 5, 7 and 10 nm. The accuracy of the model results is verified against Silvaco Technology Computer Aided Design numerical simulation results and found to be satisfactory. It is observed that by careful tuning the device parameters such as dielectric constant and dielectric thickness, lattice-matched AlInN/AlN/GaN MOSHEMT can considerably improve the device performance and suitable for high performance low distortion RF applications.

Fabrication of quantum dots in undoped Si/Si0.8Ge0.2 heterostructures using a single metal-gate layer

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si0.8Ge0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratio used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. The device uses only a single metal-gate layer, greatly simplifying device design and fabrication.