Random Dopant Fluctuation Research Articles

Performance Improvements of Random Dopant Fluctuation-Induced Variability in Negative Capacitance MOSFETS

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, VT,lin, VT,sat, on-current, ION, leakage current, IOFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced VT variability, it increases the total VT,lin variability as well as that for ION and IOFF.

Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Investigation of the Effects and the Random-Dopant-Induced Variations of Source/Drain Extension of 7-nm Strained SiGe n-Type FinFETs

In this paper, we simulated the effects of the source/drain extensions (SDEs) of the 7-nm strained SiGe n-type FinFETs and the random dopant fluctuations (RDFs) therein by TCAD tools. First, we simulated different SDE lengths and doping concentrations to examine their effects on the device characteristics. Second, we simulated the RDF in SDE to examine the device variability. Simulation results show that increasing the SDE length and decreasing the SDE doping concentration are beneficial for the device characteristics. For the device variability, increasing the SDE length and decreasing the SDE doping concentration reduce the threshold voltage variation (σ V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), on-current variation (σI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), and off-current variation (σ I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ). Therefore, the SDE optimization is critical for both the device performance and the device variability of the 7-nm FinFETs.

Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

The impact of random dopant fluctuation (RDF) on n-type Ge junctionless FinFETs (JLFETs) with metal–interlayer-semiconductor (MIS) source/drain (S/D) contact structure is firstly investigated via 3-D technology computer aided design (TCAD) simulations. The estimation and evaluation of standard deviations in threshold voltage (Vth), on-state current (Ion), off-state current (Ioff), subthreshold swing (SS), and drain induced barrier lowering (DIBL) by different Ge nanowire doping concentrations and different heights for RDF effects are performed. The results show a decreasing trend of RDF with lower doping concentration of the device. Furthermore, the influence of MIS S/D on RDF of n-type Ge JLFET is assessed through a comparative analysis between an n-type Ge JLFETs with and without MIS S/D structure. The analysis results estimate that MIS S/D can reduce performance variation to approximately 0.0237 V for ${\sigma }~\text{V}_{\mathrm{ th}}$ , 5.75 $\times \,\,10^{-5}$ A/ $\mu {\mathrm{ m}}$ for ${\sigma }~\text{I}_{\mathrm{ on}}$ , 4.30 $\times \,\,10^{-10}$ A/ $\mu {\mathrm{ m}}$ for ${\sigma }~\text{I}_{\mathrm{ off}}$ , 0.548 mV/dec for ${\sigma }$ SS, and 12.3 mV/V for DIBL, without severe performance degradation of the current nominal values. This estimation gives a significant insight on variability prediction of the 7 nm n-type Ge JLFET device with MIS S/D structure.

Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering

Currently, fin-field-effect-transistors (FinFETs) are used at 7 nm technology node, in order to avoid parasitic leakage channel under the controlled channel punch-through-stopper (PTS) doping is used with the bulk Silicon substrate (PTS-Si substrate). The dopants from PTS doping enters into the channel during the annealing process and increases channel doping level. The increased doping concentration in channel causes undesirable effects such as reduction in channel mobility and increase in random-dopant-fluctuations (RDFs). Using a silicon-on-insulator (SOI) substrate is a costlier solution, this work presents super-steep-retrograde-silicon (SSR-Si) substrate as a better solution for this problem. In this work, the SSR-Si substrate is achieved by placing lightly doped 10 nm thick SSR-buffer layer (silicon) on top of PTS-Si substrate. This SSR-buffer layer captures dopants intruding from PTS doping into channel thereby achieves SSR doping profile in the channel. The results show SSR-Si substrate reduces the RDF induced threshold variations by 50%, it also provides better DC and RF/analogue metrics than PTS-Si substrate and comparable with SOI substrate.

Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes. As the device is free from physical doping, the problems associated with random dopant fluctuations will be eliminated in the proposed doping-less topology. Our simulation results show that a programming window of 28.7 $\mu \text{A}/\mu \text{m}$ at a gate length of 10 nm with the retention time of 466 ms at 27 °C and 79 ms at 85 °C can be achieved with the proposed doping-less 1T-DRAM, which is much better than a conventional charge-plasma based doping-less 1T DRAM.

Dopingless 1T DRAM: Proposal, Design, and Analysis

In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by drift-diffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration.

Leakage Suppression Approaches in Bulk FinFETs

The Bulk FinFETs are preferred due to its low wafer cost, less defect density and less heat transfer even though the substrate leakage problem will turn up. Technological complexity and mobility degradations prevent the usage of substrate doping and variation in isolation oxide thickness to reduce off current. Stack gate technology bring down the leakage by using two gate materials with undoped substrate which is free from random dopant fluctuations. The corner effect of bulk FinFET is minimised by using corner implantation and an optimal design of FinFET is obtained. Structure with different high-k dielectric spacers is analysed to see the device performance on 3-D TCAD device simulator. It is observed that as the dielectric constant increases, performance also increases which is a requisite for low power application of the bulk FinFET.

Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering

Currently, fin-field-effect-transistors (FinFETs) are used at 7 nm technology node, in order to avoid parasitic leakage channel under the controlled channel punch-through-stopper (PTS) doping is used with the bulk Silicon substrate (PTS-Si substrate). The dopants from PTS doping enters into the channel during the annealing process and increases channel doping level. The increased doping concentration in channel causes undesirable effects such as reduction in channel mobility and increase in random-dopant-fluctuations (RDFs). Using a silicon-on-insulator (SOI) substrate is a costlier solution, this work presents super-steep-retrograde-silicon (SSR-Si) substrate as a better solution for this problem. In this work, the SSR-Si substrate is achieved by placing lightly doped 10 nm thick SSR-buffer layer (silicon) on top of PTS-Si substrate. This SSR-buffer layer captures dopants intruding from PTS doping into channel thereby achieves SSR doping profile in the channel. The results show SSR-Si substrate reduces the RDF induced threshold variations by 50%, it also provides better DC and RF/analogue metrics than PTS-Si substrate and comparable with SOI substrate.

Analytical Modeling of Charge Plasma-Based Optimized Nanogap Embedded Surrounding Gate MOSFET for Label-Free Biosensing

In this paper, analytical modeling of a charge plasma-based nanogap embedded surrounding gate MOSFET biosensor for label-free biosensing has been presented and verified with extensive simulated device data. Along the channel, considering parabolic potential profile, surface potential,threshold voltage,and drain currents have been modeled. Sensitivity has been analyzed by measuring the shift in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> and threshold voltage when the biosensor interacts with the neutral or charged biomolecules. Less thermal budgeting scheme with simplified fabrication process flow, i.e., no ion implantation or diffusion can be achieved easily here due to new charge plasma concept. In addition, the issues related to the doping control and random dopant fluctuations have been reduced significantly to make the device immune to the process variation. Hence, the proposed device has been optimized for the enhancement in device electrostatics and sensitivity. Extensive TCAD simulations have been performed to investigate the device parameters and to verify the model data. Hence, the proposed model can be considered as an optimal model of a biosensor for the future reference.

Statistical Analysis of Threshold Voltage Variation Using MOSFETs With Asymmetric Source and Drain

Threshold voltage variation is considered to be caused by various factors, such as random dopant fluctuation, surface roughness, metal gate granularity, and so on. Its magnitude ( $\sigma {V}_{\mathrm {th}}$ ) is proportional to the reciprocal of the square root of the gate area in conventional rectangular transistors. In this letter, the statistical analysis of the threshold voltage variation of trapezoidal and octagonal transistors that have asymmetric gate widths at source and drain side was discussed, in addition to the rectangular transistors. From the statistical analysis, it is experimentally demonstrated that $\sigma {V}_{\mathrm {th}}$ is correlated with the gate width at source side ( ${W} _{S}$ ), not average gate width ( ${W} _{\mathrm {ave}}$ ) which determines the gate area. Therefore, it is considered that $\sigma {V}_{\mathrm {th}}$ is characterized by the common parameter of ${W} _{S}$ even if the main factor of the threshold voltage variation would be changed.

Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance

To achieve a steep subthreshold slope (SS) and a better \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio is a major concern for switching applications in semiconductor devices. To overcome these issues, the tunnel field effect transistor (TFET) is a promising device, as it has low leakage current and a low subthreshold slope at room temperature, making it a highly useful device for ultra-lower circuit applications. However, physical doping leads to random doping fluctuations, which is a serious issue in device technology. For this purpose, we report an electrically doped TFET with a metal strip implanted in the oxide layer between the channel/source junction to improve the performance of the device in terms of steep SS and \(I_\mathrm{ON}/I_\mathrm{OFF}\) at very small gate voltage. Furthermore, we have considered the appropriate length and work function of the metal strip to maintain the improved SS and \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio. The introduction of a metal strip in the oxide layer on a conventional device offers a higher \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio on the order of \(10^{8}\), steep subthreshold slope (Point \(\hbox {SS} = 8.07\) mV/decade) and significant change in analog/RF performance. The analog/RF figures of merit are observed in terms of transconductance (\(g_{m}\)), gate-to-drain capacitance (\(C_\mathrm{gd}\)), cutoff frequency (\(f_{T}\)), and gain bandwidth product. The proposed device would be very useful for ultra-low power and high frequency circuit applications at low gate voltages. All simulated results are carried out using 2-D ATLAS software.

Evaluation of statistical variability and parametric sensitivity of non-uniformly doped Junctionless FinFET

Below 22-nm technology node, the random variation has become serious issue during dimensional scaling of the device. In this work, the impact of random discrete dopant fluctuations (RDF), gate oxide thickness variations (OTV), and metal work function variations (WFV) in non-uniformly doped Junctionless FinFET structure has been investigated using three dimensional TCAD simulations on large statistical ensemble. Furthermore, this work explores the sensitivity of the device design parameters. The simulation results when contrasted with uniformly doped Junctionless FinFET structure highlight the advantages of non-uniformly doped channel design.

Analysis and Modeling of Current Mismatch in Laterally Nonuniform MOSFETs

We present an analytical modeling approach for drain current ( ${I}_{D}$ ) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device.

Effective approach to enhance DC and high‐frequency performance of electrically doped TFET

The need to overcome the shortcomings of conventional tunnel field-effect transistor (TFET) has driven many to come up with advanced TFET innovations. This Letter presents a comparative analysis of new techniques to enhance DC/radio-frequency (RF) performance of dopingless TFETs. In this regard, two advanced structures have been compared along with conventional electrically doped TFET. The devices – electrically doped TFET, low work-function strip electrically doped TFET and low work-function live strip electrically doped TFET are investigated in terms of DC, RF and linearity. This Letter focuses on electrical doping on dopingless substrate to reduce random dopant fluctuations and fabrication complications. The comparative analysis illustrates the importance of low work-function live strip (LWLS) over low work-function strip (LWS). In addition, an optimisation of length and position of LWS and LWLS is also investigated for providing fabrication ease.

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant “number” and dopant “position” fluctuation in channels is proposed. A new model of σVth,num caused by “number” is given and the method of obtaining the “position” influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon–Germanium Channel pFET

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ( $\text{V}_{T}$ ) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ ) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages.

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.