Random Dopant Fluctuation Research Articles

A novel dynamically configurable electrostatically doped silicon nanowire impact ionization MOS

In this paper, a novel dynamically configurable, electrostatically doped silicon nanowire impact ionization MOS (E-SiNW-IMOS) based on dopant-free technology is investigated. The key attribute of the proposed device is its polarity controlled dynamic reconfigurability of charge gating mechanism from impact ionization to band-to-band tunneling. This ensures that same device can act as E-SiNW-IMOS or electrostatically doped silicon nanowire Tunnel FET (E-SiNW-TFET) depending on bias conditions. It consists of an undoped SiNW and three independent all-around-gates two polarity gates to realize n+ and p+ regions in undoped nanowire by electrostatic doping and a control gate to initiate impact ionization/tunneling. Combination of biases applied at polarity gates and control gate configures both the operating mechanism and device polarity. This enables the potential co-integration of IMOS (offering high gain and ultra steep switching behavior) and TFET (with extremely low leakage current and power-efficiency) on a single chip. A calibrated 3-D TCAD study reveals consistent static device behavior for both the devices considered. It offers a simplified fabrication process as it avoids the need of ion implantation and thermal annealing, thereby reducing thermal budget. Further, it is highly resilient towards process variations, doping control issues, voltage variations and random dopant fluctuations (RDF).

Junctionless Silicon and In0.53Ga0.47As Transistors—Part II: Device Variability From Random Dopant Fluctuation

Random dopant fluctuation (RDF) variability in nanoscale junctionless FETs (JLFETs) utilizing either Si or In0.53Ga0.47As channels has been studied using technology computer-aided design (TCAD) simulations. The 15nm node Si and InGaAs JLFETs are equivalently designed and calibrated using nonequilibrium Green’s function simulations for statistical TCAD analysis. We find that n-InGaAs JLFETs exhibit reduced RDF variability compared with n-Si JLFETs in terms of threshold voltage, subthreshold swing, and drain-induced barrier lowering as a result of high degeneracy effects. By contrast, the variability of p-InGaAs JLFETs is comparable with that of n- and p-Si JLFETs because of the larger valence band density of states (DOS). The normalized variations in ON-state drive current are roughly equal ( $\sim 16$ %) for all device types, because the major effects of degenerate screening on current transport effectively cancel one another. From these results, we find that high carrier degeneracy in small DOS materials can have a significant effect on the electrostatic integrity of JLFETs in the presence of RDF (especially in subthreshold), and that degenerately doped n-InGaAs devices are slightly (and inherently) more immune to RDF compared with Si JLFETs.

A novel process variation immune dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z $$^{2}$$ 2 FET) based on transition metals

Transition metal (TM) electrodes based dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z$$^{2}$$2FET) is reported in this paper. The work-function engineering of TM electrodes is used for charge plasma based electrostatic pseudo doping. Work-function difference between TM electrodes and the undoped silicon film induces p$$^{+}$$+ and n$$^{+}$$+ regions in the film. TMs exhibit easy tunability of work-function and their CMOS fabrication compatibility pledges for their potential applications as these electrodes. A technology computer-aided design simulation study is performed to provide physical insight into its working mechanism and performance. It exhibits all the inherent characteristics of conventional Z$$^{2}$$2FET, viz. zero slope switching, high $$I_{ON}/I_{OFF}$$ION/IOFF ratio, lower operating voltages, immunity towards hot electron degradation and gate controlled hysteresis. The detrimental doping control issues, mobility degradation due to heavy doping and statistical random dopant fluctuations can no more obviate the device performance, it results in more process variations immune design. Hence it can be a potential fast switching transistor.

The effect of random dopant fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.

(Invited) Variability in FinFET SRAM Cells

Recently, variability of the devices due to the various random sources is increasing and will reduce the yield of the circuit. To overcome these problems, FinFET device technologies have been proposed and investigated for many years. They have an intrinsic strength against the SCE and they allow the use of intrinsic channel and thus reduce the random dopant fluctuation. However, variability of the FinFET still remains. Variations are caused by fluctuations of the gate-length (ΔLG), the fin-width (ΔTFin), the oxide thickness (ΔTox), the line edge roughness of fin and gate electrodes. In addition to these variations, a new source of variation is generated through an introduction of the metal gate (MG) due to the dependency of the work function (WF) on the orientation of metal grains. To understand the origin of the Vth variation in the MG FinFET, we experimentally evaluate the effect of the ΔLG, ΔTFin, and ΔTox to the Vth variation by measuring the standard deviation of these values. The standard deviations of the dimension variation sources such as the ΔLG and ΔTFin were measured by counting the statistical distribution of the size using a scanning electron microscope (SEM). The same chip is used after the electrical measurements. The ΔTox variation was measured by ellipsometry using (110) oriented test wafers which have the same orientation with the side-wall channel of the FinFET. It is revealed that the ΔLG, ΔTFin, and ΔTox contributions to the Vth variation are insignificant since their standard deviations and partial derivatives are small. Thus, it is concluded that the main variation source of the TiN MG FinFET is the work function variation (WFV) of the TiN. The observed deviation of 30 mV is almost the same value with the previous reports. The possible explanation of the WFV is an over 200 mV work function difference between (100) and (111) oriented grains of TiN and there is also an additional WFV due to the composition or nitrogen concentration of the TiN. Moreover, we have developed and introduced amorphous metal gate into FinFET for the first time using the TaSiN metal gate to overcome the work function variation in the metal gate. The TaSiN gates exhibit smaller variability than that of TiN and the record smallest variability is realized. The Vth variation will directly cause the variation in the SRAM performance. To overcome the variation problem, we have developed independent doubl-gate (IDG) FinFET SRAM technologies. We have developped two types of FinFET SRAM cells using the IDG-FinFET. One is a flexible-Vth (Flex-Vth) SRAM cell and the other is a flexible pass-gate (Flex-PG) SRAM cell. In the Flex-Vth cell, all the transistors in the cell are composed by the IDG-FinFET. The Vth of the all transistor can be controlled by the external bias to the Vth-control-gate. The real values of Vth can be tuned keeping the symmetry of Vth. Thus, the stand-by leakage current and the short circuit current of the cell are dynamically controlled. For the Flex-PG cell, IDG-FinFETs are used only for the PG and the other transistors are composed by the common-DG FinFET. The Ion ratio of the pull down to the pass gate which corresponds to the β-ratio is thus flexibly changed. A great enhancement of the read margin is experimentally confirmed for the Flex-PG cell. Moreover, significant reduction of the variation in the SRAM characteristics is clearly demonstrated. Finally, scalability of the Flex-PG SRAM technology is evaluated by the compact model analysis. Device parameters including variations are satisfactory to the ITRS roadmap. The result shows that the TaSiN gate and the Flex-PG technology enable 12.5-nm-LG SRAM with the sufficient static noise margin.

Dopingless impact ionization MOS (DL-IMOS)—a remedy for complex process flow

We propose a unique approach for realizing dopingless impact ionization MOS (DL-IMOS) based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.

Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

In this work the sensitivity of process parameters like channel length (L), channel thickness (tSi), and gate work function (φM) on various performance metrics of an undoped cylindrical gate all around (GAA) metal-oxide-semiconductor field effect transistor (MOSFET) are systematically analyzed. Undoped GAA MOSFET is a radical invention as it introduces a new direction for transistor scaling. In conventional MOSFET, generally the channel doping concentration is very high to provide high on-state current, but in contrary it causes random dopant fluctuation and threshold voltage variation. So, the undoped nature of GAA MOSFET solves the above complications. Hence, we have analyzed the electrical characteristics as well as the analog/RF performances of undoped GAA MOSFET through Sentaurus device simulator.

Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor

A variation-immune symmetric tunnel field-effect transistor (S-TFET) is proposed for the first time to implement bidirectional current flows ( $I_{\mathrm{{\scriptstyle ON}}}=3.6~\mu $ A/ $\mu $ m, $I_{\mathrm{{\scriptstyle OFF}}}=23$ pA/ $\mu $ m at $V_{\mathrm {DD}}= 0.5$ V) with the steep-switching feature of a subthreshold slope (SS) $ mV/dec ( ${\rm SS} = 47$ mV/dec) and to alleviate the impact of random variation. A random variation analysis with the three major random variation sources, i.e., line-edge roughness, random dopant fluctuation, and work-function variation, is performed to quantitatively evaluate the impact of each variation source on the performance of the device. To perform variation-aware design for the S-TFET, the key device parameter (i.e., the thickness of the intrinsically doped silicon pad layer) is optimized to minimize the impact of random variation on the threshold voltage ( $V_{T}$ ) and SS. For ultralow power applications with a sub-0.5 V power supply voltage ( $V_{{\rm {DD}}}$ ), the variation-robust S-TFET is one of several promising device structures.

Germanium Junctionless MOSFET with Steep Subthreshold Swing

Over the past few decades, the classical Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has undergone aggressive scaling, and ultimately reached its scaling limits due to inherent short channel effects, random dopant fluctuations and increased parasitics [1]. The downscaling is foreseen to continue with multiple gate structures, but at the expense of increased parasitics and challenges in steep source/drain junctions. The Junctionless (JL) multiple gate MOSFET, overcomes these limitations as it does not require any pnjunction and is easy to fabricate [2]. Apart from the potential for low power logic, analog and RF applications, JL MOSFETs exhibit steeper Subthreshold Swing (S-swing) due to impact ionization phenomena at relatively lower drain voltages in comparison to conventional inversion mode transistors [3]. The steep S-swing for symmetric gate operation in silicon Double Gate (JL) was obtained at a drain bias (V ds) of 2 V. A possible option to reduce the V dsrequired to trigger impact ionization is to use a lower bandgap material such as Germanium (Ge), which is also considered as strong candidate for future devices due to higher carrier mobility. In this work, Ge JL Double Gate (DG) n-channel MOSFETs (figure 1) have been studied using ATLAS simulation tool [4]. Our simulation results, published earlier [5-6], for silicon JL MOSFETs depicting steep S-swing, hysteresis, increase in the number of decades of drain current transition with applied drain bias are in good qualitative agreement with the experimental results on silicon JL transistors [3]. In this work, we focus on Ge JL transistors and analyze the impact of impact ionization for achieving steep S-swing values at low drain bias. Our results (figure 2) show an impact ionization triggered steep transition in the subthreshold current with an ideal S-swing (< 1 mV/decade) at a drain bias of 1.3V. The phenomenon of impact ionization in Ge JL MOSFETs is analyzed in terms of Generation-Recombination (G-R) rates and the product of current density and electric field (J.E). Results show that a current transition of nearly 3.5 is achieve in Ge JL MOSFETs at the onset of steep S-swing while the same is limited an order in Si JL transistors. Ge based devices also exhibit a higher value of (J.E) which is directly correlated with the higher degree of impact ionization in the device. The work demonstrates new opportunities for achieving steep subthreshold swing at relatively lower drain voltages in emerging technologies. Acknowledgement: This work is supported in part by University Grants Commission, Government of India, through the Junior Research Fellowship (JRF) award to Manish Gupta (Ref.: 4015/NET-June2013), and in part by the Science and Engineering Research Board, Department of Science and Technology, Government of India, under Grant SR/S3/EECS/0130/2011.

Screening small-delay defects using inter-path correlation to reduce reliability risk

Subtle defects such as low resistive vias and high resistive shorts cause Small-Delay Defects that are hard to detect even by advanced test methodologies. Detection of these defects aggravates with process variations becoming an important source of test escapes. Furthermore, these defects may degrade with time posing a reliability risk. In this paper, a novel methodology to detect SDDs in the presence of process variations using delay correlation information between logic paths of a circuit is proposed. This methodology exploits the concept that for two correlated paths, a part of the delay variance in one path can be described by the delay variance in other path. Using multiple path prediction allows to further improve the detection of SDDs. A path-based statistical timing analysis framework has been developed and implemented to compute timing information and inter-path correlation. Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in ISCAS85 benchmark circuits show that the proposed methodology is able to detect SDDs in the slack interval and to distinguish delay defects from process variations. The obtained results give indication of the promising capabilities of the proposed technique to detect “very” small-delay defects. Hence, test quality is improved leading to higher product reliability.

Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants.

In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16-nm-gate trapezoidal bulk fin-type field effect transistor (FinFET) devices. The fixed top-fin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed top-fin width, we explore the impact of geometry and RDF on the on-/off-state current and the threshold voltage (Vth) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the off-state current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the short-channel effect and Vth variation degrade as the fin angle is getting smaller. The magnitude of the normalized σVth increases 7% when the fin angle decreases from 90° to 70°.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Hybrid methodology to model random dopant fluctuations in low doped FinFETs

A hybrid approach to model the effect of random dopant fluctuations in low doped FinFETs is proposed. Existing Monte Carlo and atomistic approaches are found to be inadequate to capture device variability correctly when applied independently. Instead a hybrid methodology which uses an atomistic approach in low doped regions and Monte Carlo everywhere else is developed. The hybrid approach is shown to capture the threshold voltage variability adequately. Comparison with analytical results for planar MOSFETs shows an excellent agreement and establishes the validity of the approach. The results suggest that accurate modeling of low doped regions is essential to be able to estimate variability correctly.

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate all Around Nanowire n-MOSFET

In this brief, the random dopant fluctuation (RDF)-induced threshold voltage (VT) variability, ON current (ION) variability, and VT mismatch in undoped channel Si gate-all-around (GAA) n-nanowire MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The RDFs are introduced in the Si NWFET tetrahedral device grid by a 3-D atomistic MonteCarlo technique. The RDF due to discrete random dopants located in the source (S)/drain (D) extension and channel regions of Si GAA n-NWFET are found to impact the device characteristic variability. The numerical VT mismatch analysis and comparison with the Si n-NWFET total AVT measurement data from the literature reveal that RDF still plays a significant source for device random fluctuations in undoped channel Si GAA n-NWFETs. The numerical VT mismatch study indicates the fact that complete suppression of RDF induced device random variability in undoped channel fully depleted MOS devices is still going to be a challenge, as long as doped S/D regions are employed.

Comparison Between Bulk and FDSOI POM Flash Cell: A Multiscale Simulation Study

In this brief, we present a multiscale simulation study of a fully depleted silicon-on-insulator (FDSOI) nonvolatile memory cell based on polyoxometalates (POMs) inorganic molecular clusters used as a storage media embedded in the gate dielectric of flash cells. In particular, we focus our discussion on the threshold voltage variability introduced by random discrete dopants (random dopant fluctuation) and by fluctuations in the distribution of the POM molecules in the storage media (POM fluctuation). To highlight the advantages of the FDSOI POM flash cell, we provide a comparison with an equivalent cell based on conventional (BULK) transistors. The presented simulation framework and methodology is transferrable to flash cells based on alternative molecules used as a storage media.

Analytical modeling of cutoff frequency variability reserving correlations due to random dopant fluctuation in nanometer MOSFETs

Correlations are concerned for modeling of CMOS devices and circuits variability when using back propagation of variations (BPV) methodology in the paper. Strong reverse correlations are observed and investigated between variation parameters, particularly for threshold voltage (VT), total gate capacitance (Cgg) and trans-conductance (gm), on gate voltage dependence due to random dopant fluctuation (RDF) in nanometer MOSFETs. These correlations are verified both in theoretical and simulation approaches. Based on these correlations, a simple and accurate analytical model for capturing fT variability is proposed. The model is in good agreement with HSPICE Monte Carlo simulations in different design decisions such as effective width length ratios, source voltages and doping concentrations. Results show the estimation errors are not more than −2.33% and 1.30% for NMOS and PMOS, respectively. Furthermore, our analysis of the correlation and analytical formula are still effective for the continued scaling CMOS technology.

Upper/lower-side random dopant fluctuation on 16-nm-gate HKMG bulk FinFET

In this work, we for the first time classify dopants that exist near the source/drain side or the upper/lower side of silicon fin and explore the impact of random dopants' (RDs) position on devices' DC characteristic. The effects of random dopant fluctuation (RDF) on the performance of 16–nm–gate HKMG bulk FinFET are studied by using experimentally validated three–dimensional RDF device simulation. The dopants near the source side or the upper fin would induce large barrier for electrons, so the threshold voltage (Vth) will be increased in n–type HKMG bulk FinFET devices which have more dopants on the source side or the upper fin. In addition, the upper–fin's dopants are discovered to have larger influence on the profile of energy band. Moreover, the issue about Vth's fluctuation on both the planar MOSFET and the bulk FinFETs with different aspect ratios (AR) is studied. The higher–AR HKMG bulk FinFET devices have relatively smaller Vth's variation induced by RDF.

A 16 nm 128 Mb SRAM in High-&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\kappa$&lt;/tex&gt;&lt;/formula&gt; Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM VDDMIN. However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse write-VDDMIN issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from VDD to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write VDDMIN: 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell VDD (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement lower-cell-VDD (WRE-LCV) scheme for write assist without the concern of reliability at higher VDD operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with 0.07μm2 area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall VDDMIN improvement can be over 300mV in a 128Mb SRAM test-chip.

Charge‐plasma‐based super‐steep negative capacitance junctionless tunnel field effect transistor: design and performance

A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (L D). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (g m) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.