Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants.

Wen-Tsung Huang,Yiming Li

doi:10.1186/s11671-015-0739-0

Wen-Tsung Huang, Yiming Li

Open Access

https://doi.org/10.1186/s11671-015-0739-0

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Abstract

In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16-nm-gate trapezoidal bulk fin-type field effect transistor (FinFET) devices. The fixed top-fin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed top-fin width, we explore the impact of geometry and RDF on the on-/off-state current and the threshold voltage (Vth) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the off-state current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the short-channel effect and Vth variation degrade as the fin angle is getting smaller. The magnitude of the normalized σVth increases 7% when the fin angle decreases from 90° to 70°.

Highlights

Scaling down the CMOS technology node beyond the sub-20 nm causes the transistor to go through a transition from planar to multi-gate FETs such as bulk fin-type field effect transistors (FinFETs) because of the requirement of better gate control and suppression on short-channel effects (SCEs) [1,2,3]
To ensure the best accuracy of device simulation, the ID-VG curve of the FinFET at VD = 0.8 V is experimentally calibrated with measured data, as shown in Figure 3, where the extracted physical and process parameters are used for the following study
random dopant fluctuation (RDF) on trapezoidal bulk FinFET devices with the fixed top-fin width (Wtop) and different fin angles is studied by experimentally validated 3D device simulation

Summary

Introduction

Scaling down the CMOS technology node beyond the sub-20 nm causes the transistor to go through a transition from planar to multi-gate FETs such as bulk fin-type field effect transistors (FinFETs) because of the requirement of better gate control and suppression on short-channel effects (SCEs) [1,2,3]. In addition to the improvement on DC characteristics of individual device, continuously scaling overcomes challenges on fabrication and suppresses systematic variation and random effects [4,5]. The actual fins channel may be fabricated as trapezoidal shape and degrade the device performance by significant SCEs. For variability issues, there are many serious fluctuation sources such as random dopant fluctuation (RDF) [7], work-function. We explore the RDF on DC characteristics of 16-nm-gate trapezoidal bulk FinFETs with the fixed top-fin width (Wtop) condition. The ‘Methods’ section introduces the simulation technique for studying the RDF on trapezoidal bulk FinFET devices

Methods

Results

Conclusion