Study of threshold voltage fluctuation caused by source and drain extensions doping variation of tri-gate fin-type FET using three-dimensional device simulation

Abstract

The threshold voltage (Vth) fluctuation becomes an emergency problem in the design of integrated circuits using scaled silicon transistors. Since the Vth fluctuation caused by random dopant fluctuation (RDF) in the channel region becomes seriously large, the RDF-induced Vth fluctuation has been studied so far. Although the tri-gate fin-type field-effect transistor (FinFET) is promising owing to the RDF-free intrinsic channel, the Vth fluctuation caused by source and drain extensions doping variation (SDEDV) has not been investigated yet. Therefore, we studied the SDEDV-induced Vth fluctuation of the tri-gate FinFET by three-dimensional (3D) device simulation for the first time. It is demonstrated first that 3D simulation is required for possible accurate analysis. Then it is shown that the SDEDV based on Gaussian doping causes a large Vth fluctuation with a standard deviation of 4.2 mV in the case of the tri-gate FinFET. The origin of the SDEDV-induced Vth fluctuation is the broadening variation of the 3D Gaussian doping profile in the source–drain direction. This result indicates that the broadening suppression of impurity in the ion-implantation and annealing processes is very important for the SDEDV-induced Vth fluctuation.