Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations

Abstract

The threshold voltage (Vth) fluctuation induced by the ion implantation to the source and drain extensions (SDE) of a silicon-on-insulator (SOI) triple-gate (tri-gate) fin-type field-effect transistor (FinFET) was analyzed for the first time with the use of realistic positional information of discretely doped ions by both three-dimensional (3D) process and device simulations. Interestingly, it was found that the Vth fluctuation induced by SDE ion implantation has a very low and broad distribution on the low-Vth side even in the case of a robust device structure such as SOI tri-gate FinFET. Furthermore, for the first time, it was quantitatively demonstrated using a proposed cluster percolation model that the origin of the very low and broad Vth fluctuation is the conductive percolation among unintentionally doped ions in the channel region of the device. These results would contribute to the realization of robust transistors.