Three-dimensional exploration of the origin of threshold voltage fluctuation of silicon-on-insulator triple-gate fin-type field-effect transistors caused by ion implantation to source and drain extensions

Abstract

The origin of the Vth fluctuation induced by ion implantation (I/I) into the source and drain extensions (SDEs) of triple-gate (tri-gate) fin-type field-effect transistors has been three-dimensionally explored by both three-dimensional (3D) process and device simulations. The 3D electrostatic potential distributions in the whole Si channel fin are analyzed, and it is confirmed that the 3D electrostatic potential distribution of the lowest Vth sample is more undulated than that of the highest Vth sample due to implanted arsenic (As+) ions to the SDEs irrespective of the drain bias condition. We found also that the minimum of bottleneck barrier heights (BBHs) in the Si whole channel fin, which is called BBH3D,min, is strongly correlated with the Vth, and therefore is a strong indicator to study the Vth of the device. It now became obvious that the origin of the SDE I/I-induced Vth fluctuation is a variation of BBH3D,min in the whole channel for the first time. The obtained results are beneficial for the research and development of such future devices.