Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor

Abstract

A variation-immune symmetric tunnel field-effect transistor (S-TFET) is proposed for the first time to implement bidirectional current flows ( $I_{\mathrm{{\scriptstyle ON}}}=3.6~\mu $ A/ $\mu $ m, $I_{\mathrm{{\scriptstyle OFF}}}=23$ pA/ $\mu $ m at $V_{\mathrm {DD}}= 0.5$ V) with the steep-switching feature of a subthreshold slope (SS) $ mV/dec ( ${\rm SS} = 47$ mV/dec) and to alleviate the impact of random variation. A random variation analysis with the three major random variation sources, i.e., line-edge roughness, random dopant fluctuation, and work-function variation, is performed to quantitatively evaluate the impact of each variation source on the performance of the device. To perform variation-aware design for the S-TFET, the key device parameter (i.e., the thickness of the intrinsically doped silicon pad layer) is optimized to minimize the impact of random variation on the threshold voltage ( $V_{T}$ ) and SS. For ultralow power applications with a sub-0.5 V power supply voltage ( $V_{{\rm {DD}}}$ ), the variation-robust S-TFET is one of several promising device structures.