An Investigation on the Effect of LER on Threshold Voltage and On Current of SOI, Bulk and GAA FinFETs

Abstract

A device level way to quantitatively assess the influence of Line Edge Roughness (LER) on different fin based structures is considered. We know FinFETs have high drive current and offer better control over leakage and short channel effects. The FinFET device parameters such as On-current, Off-current and threshold voltage are impressionable to structure of FinFET. Performance of the 3D FinFET structures affected by LER. LER is referred to as randomly varied edges or roughness in printed pattern edge. The effect of LER in some cases results in reduction of leakage current, but in some cases it worsened the device parameter. The brunt of random variation sources on the electrical characteristics of the devices are not easy to be discriminated from each other. Random dopant fluctuations (RDF), Metal Gate Granularity (MGG) and Line Edge Roughness (LER) are the severe random variations which enforce restraints on the FinFET. Here an investigation on the effect of LER on the threshold voltage and On-current of SOI, Bulk and GAA FinFET is proposed. A comparative study on different structures is also presented. All simulations are carried out in Silvaco Atlas TCAD.