Random Access Memory Bit Research Articles

Stability Parameters of Register File Bit Cell with Low Power Consumption Priority

This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm2.

IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch

Spin switch (SS) is a promising spintronic device which exhibits compactness, low power, non-volatility, input–output isolation leveraging giant spin Hall effect, spin transfer torque, and dipolar coupling. In this paper, we propose a novel device-to-architecture co-design for an in-memory computing platform using coterminous SS (IMCS2), which could simultaneously work as non-volatile memory and reconfigurable in-memory logic (AND/NAND, OR/NOR, and XOR/XNOR) without add-on logic circuits to memory chip. The computed logic output could be simply read out like a normal magnetic random access memory bit cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in the conventional von Neumann computing system. The IMCS2-based in-memory bulk bitwise Boolean vector operation shows ${\sim }9\times $ energy saving and ${\sim }3\times $ speedup compared with that of DRAM-based in-memory computing platform. We further employ in-memory multiplication to evaluate the performance of the proposed in-memory computing platform for vector–vector multiplication with different vector sizes.

Enhanced ferromagnetic resonance linewidth of the free layer in perpendicular magnetic tunnel junctions.

We report the frequency dependence of the ferromagnetic resonance linewidth of the free layer in magnetic tunnel junctions with all perpendicular-to-the-plane magnetized layers. While the magnetic-field-swept linewidth nominally shows a linear growth with frequency in agreement with Gilbert damping, an additional frequency-dependent linewidth broadening occurs that shows a strong asymmetry between the absorption spectra for increasing- and decreasing external magnetic field. Inhomogeneous magnetic fields produced during reversal of the reference and pinned layer complex is demonstrated to be at the origin of the symmetry breaking and the linewidth enhancement. Consequentially, this linewidth enhancement provides indirect information on the magnetic coercivity of the reference and pinned layers. These results have important implications for the characterization of perpendicular magnetized magnetic random access memory bit cells.

Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

Bit failure events induced by random telegraph noise (RTN) for silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells were characterized by directly monitoring the storage node voltage of individual cells, using a device-matrix-array (DMA) test element group (TEG). Correlating the cell-level RTN and failure waveforms with the RTN waveforms of individual transistors that constitute the same cell, RTN of a specific transistor that causes the cell failure was identified.

Thermally-Assisted Spin-Transfer Torque Magnetization Reversal of Uniaxial Nanomagnets in Energy Space

The asymptotic behavior of switching time as a function of current for a uniaxial macrospin under the effects of both spin-torque and thermal noise is explored analytically by focusing on its diffusive energy space dynamics. The scaling dependence ($I\rightarrow 0$, $<\tau\propto\exp(-\xi(1-I)^2)$) is shown to confirm recent literature results. The analysis shows the mean switching time to be functionally independent of the angle between the spin current and magnet's uniaxial axes. These results have important implications for modeling the energetics of thermally assisted magnetization reversal of spin transfer magnetic random access memory bit cells.

Thermally assisted spin-transfer torque magnetization reversal in uniaxial nanomagnets

We simulate the stochastic Landau-Lifshitz-Gilbert dynamics of a uniaxial nanomagnet out to sub-millisecond timescales using a graphical processing unit based micromagnetic code and determine the effect of geometrical tilts between the spin-current and uniaxial anisotropy axes on the thermally assisted reversal dynamics. The asymptotic behavior of the switching time (I→0, 〈τ〉∝exp(−ξ(1−I)2)) is approached gradually, indicating a broad crossover regime between the ballistic and thermally assisted spin transfer reversal. Interestingly, the functional form of the mean switching time is shown to be independent of the angle between the spin current and magnet's uniaxial axes. These results have important implications for modeling the energetics of thermally assisted magnetization reversal of spin transfer magnetic random access memory bit cells.

Asymmetric switching behavior in perpendicularly magnetized spin-valve nanopillars due to the polarizer dipole field

We report the free layer switching field distributions of spin-valve nanopillars with perpendicular magnetization. While the distributions are consistent with a thermal activation model, they show a strong asymmetry between the parallel to antiparallel and the reverse transition, with energy barriers more than 50% higher for the parallel to antiparallel transitions. The inhomogeneous dipolar field from the polarizer is demonstrated to be at the origin of this symmetry breaking. Interestingly, the symmetry is restored for devices with a lithographically defined notch pair removed from the midpoint of the pillar cross-section along the ellipse long axis. These results have important implications for the thermal stability of perpendicular magnetized magnetic random access memory bit cells.

Gate etch process model for static random access memory bit cell and FinFET construction

A reactor/feature/lithography modeling suite has been developed to study the gate etch process. The gate etch process study consists of an eight step process designed to etch through a hard mask (HM)/antireflective coating/polysilicon gate stack and a 22+ step modeled process for FinFET (field effect transistor) manufacture. Coupling to a lithography model allows for a study of how a static random access memory (SRAM) bit cell layout transfers into the gate stack during the gate etch process. The lithography model calculates a three-dimensional (3D) photoresist (PR) profile using the photomask, illumination conditions, and a PR development model. The 3D PR profile is fed into the feature model, Papaya, as the initial PR etch mask condition. The study of the cumulative effect of the gate etch process required to transfer a photomask layout into a gate stack allows for a better understanding of the impact one step in the gate etch process can have on subsequent steps in the process. Studies of pattern transfer of a SRAM bit cell into a gate stack have shown that more edge movement occurs at line ends than at line sides. The line ends are more exposed to incoming etchants and have less opportunity for passivant buildup from the etching wafer than along line sides. An increase in sidewall slope at line ends during the trim and HM etch is observed experimentally and predicted by the model. The slope at line ends during trim and HM etch is more prevalent for narrow ends versus the wider “contact” ends. The lower the PR etch mask height after the HM etch step, the larger the angle seen at line ends which increases the line end pullback. So, a correlation exists between higher wafer power during the HM etch and line end pullback. Passivant formation at the polysilicon sidewall during the main etch/soft landing/overetch polysilicon etch sequence can straighten the profile as well as cause hourglassing and trapezoidal profiles. Passivant thickness, passivant deposition rate, as well as the passivant to polysilicon etch ratio all control this profile behavior. Increased passivation levels also have the tendency to increase linewidth roughness. In FinFET manufacture the gate etch needs to account for the increased topography introduced by the fins.

Derivation and implication of a novel DRAM bit cost model

A model for the cost/performance of a large-scale integrated circuit (LSI) is derived using critical area with 1/x/sup 3/ defect size distribution and common industry trends for device parameters and process parameters. The model predicts that dynamic random access memory bit cost will begin to increase sometime after 2005, if the current bit capacity increase rate of four times every three years remains effective. It is suggested that the rate is reduced to two times every two years, which will ensure a bit cost reduction beyond 2010. However, if the defect density can be reduced faster than the past trends, a four times bit capacity increase every three years can still remain cost effective.

An Analytical Delay Model for Read Operation at Any Position on Dyamic Random Access Memory Bit Lines

In deep submicron devices, the delay of interconnect becomes comparable to that of gate, which limits the circuit performance. Thus, it seems more appropriate to model the interconnect and the gate as a single component in study the device performance. Taking this approach, we develop an analytical model for the signal for a pre-charged, deep submicron dynamic random access memory (DRAM) at any position on the bit lines for read logic-1 operation. The bit line is modeled as a distributed resistance-capacitance (RC) line and is simultaneously solved with the drain current model. The model agrees well with the simulation program integrated circuits emphasis (SPICE) simulations using Berkeley short-channel IGFET model version 3 (BSIM3) models for various values of the bit line resistance, the capacitance on both the bit line and the sense amplifier, and the cell device width.

Resolution of MOS one-transistor, dynamic RAM bit failures using SEM stroboscopic techniques

Stroboscopic techniques are used to allow the scanning electron microscope (SEM) to function as an electronic probe with a spatial resolution of 0.2 μm2 and a time resolution of 0.3 ns. The causes of ’’row’’ and ’’single-bit’’ failures in the one-transistor, dynamic random-access-memory (RAM) are resolved using the SEM electronic probe technique.