An Analytical Delay Model for Read Operation at Any Position on Dyamic Random Access Memory Bit Lines

Abstract

In deep submicron devices, the delay of interconnect becomes comparable to that of gate, which limits the circuit performance. Thus, it seems more appropriate to model the interconnect and the gate as a single component in study the device performance. Taking this approach, we develop an analytical model for the signal for a pre-charged, deep submicron dynamic random access memory (DRAM) at any position on the bit lines for read logic-1 operation. The bit line is modeled as a distributed resistance-capacitance (RC) line and is simultaneously solved with the drain current model. The model agrees well with the simulation program integrated circuits emphasis (SPICE) simulations using Berkeley short-channel IGFET model version 3 (BSIM3) models for various values of the bit line resistance, the capacitance on both the bit line and the sense amplifier, and the cell device width.