Random Access Memory Array Research Articles

One-Selector-One-Resistor Integrated Memory Cells Based on Two-Dimensional Heterojunction Memory Selectors.

Selectors are critical components for reducing the sneak path leakage currents in emerging resistive random-access memory (RRAM) arrays. Two-dimensional (2D) materials provide a rich choice of materials with van der Waals stacking to form the heterostructure selectors with controllable energy barriers. Here, we experimentally demonstrate 2D-material-based heterostructure selectors with exponential current-voltage (I-V) relationships and integrate them with hafnium oxide (HfOx)-based RRAMs, forming one-selector-one-resistor (1S1R) cells. The multilayer graphene (MG)/tungsten disulfide (WS2)/platinum (Pt) selector contains two asymmetric heterojunctions with different Schottky barriers, which lead to highly nonlinear and asymmetric I-V characteristics. The 2D selectors in 1S1R cells can successfully drive RRAMs, reduce sneak path leakage current by more than 100 times, and provide the set compliance current. The 1S1R cells are further modeled and integrated into both planar and 3D memory arrays, with circuit-level simulations demonstrating that the presence of 2D selectors in large memory arrays can reduce the power consumption by up to 86%, improve the read/write margin by up to 31%, and avoid write failure. Such a platform holds high potential for constructing 3D high-density memories and performing in-memory computing.

Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System

Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical channel-all-around structure are investigated by technology computer-aided design (TCAD) simulation. The simulated drain current–gate voltage (I DS–V GS) curves of the IGZO FeFET show an on–off ratio of up to 107 and a memory window of 1.76 V, proving that ferroelectric hafnium oxide (FE-HfO2) is suitable for a 2T0C transistor. To solve the potential current-sharing problem of the 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of FE-HfO2. This solution shows a remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of the IGZO-based FeFET on 2T0C DRAM memory cells, but also providing an array design guideline for highly reliable 2T0C memory applications.

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.

Demonstration of transfer learning using 14 nm technology analog ReRAM array

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array.

Enhancing the ubiquitous sensors and connected devices with computational abilities to realize visions of the Internet of Things (IoT) requires the development of robust, compact, and low-power deep neural network accelerators. Analog in-memory matrix-matrix multiplications enabled by emerging memories can significantly reduce the accelerator energy budget while resulting in compact accelerators. In this article, we design a hardware-aware deep neural network (DNN) accelerator that combines a planar-staircase resistive random access memory (RRAM) array with a variation-tolerant in-memory compute methodology to enhance the peak power efficiency by 5.64× and area efficiency by 4.7× over state-of-the-art DNN accelerators. Pulse application at the bottom electrodes of the staircase array generates a concurrent input shift, which eliminates the input unfolding, and regeneration required for convolution execution within typical crossbar arrays. Our in-memory compute method operates in charge domain and facilitates high-accuracy floating-point computations with low RRAM states, device requirement. This work provides a path toward fast hardware accelerators that use low power and low area.

A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)

Stochastic computing (SC) has emerged as a promising solution for performing complex functions on large amounts of data to meet future computing demands. However, the hardware needed to generate random bit-streams using conventional CMOS based technologies drastically increases the area and delay cost. Area costs can be reduced using spintronics based RNGs, however, this will not alleviate the delay costs since stochastic bit generation is still performed separately from the computation. In this paper, we present an SC method of embedding stochastic bit generation and processing in a computational random access memory array, which we refer to as SC-CRAM. We demonstrate that SC-CRAM is a resilient and low cost method for image processing, Bayesian inference systems, and Bayesian belief networks.

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations

Computing in-memory (CIM) is a promising new computing method to solve problems caused by von Neumann bottlenecks. It mitigates the need for transmitting large amounts of data between the processing and memory units, significantly decreasing the latency and energy consumption. However, writing back the calculation results for CIM can become a new bottleneck if only parallel computing is implemented. This study proposes a bidirectional static random access memory (SRAM) array structure comprising self-cycling eight-transistor (8T) cells, which can achieve full-array Boolean logic operations and read/write in two directions. The CIM results can be restored in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> bit cells in a single cycle without additional memory. In addition, any data row can be copied into another row by controlling the intermediate transistor in the 8T cell. A 16-kb SRAM was implemented in the 28-nm CMOS technology to verify the effectiveness of the proposed design. The throughput of the proposed CIM macro is 1851.4 GOPS. Compared with the existing CIM macros, the throughput increased 3–56.6 times and the energy efficiency was as high as 270.5 TOPS/W at a supply voltage of 0.66 V. When the proposed circuits were applied to advanced encryption standard (AES) algorithms, the energy efficiency is increased by about 47.5%–63% compared to the von Neumann architecture.

Analysis of VMM computation strategies to implement BNN applications on RRAM arrays

The growing interest in edge-AI solutions and advances in the field of quantized neural networks have led to hardware efficient binary neural networks (BNNs). Extreme BNNs utilize only binary weights and activations, making them more memory efficient. Such networks can be realized using exclusive-NOR (XNOR) gates and popcount circuits. The analog in-memory realization of BNNs utilizing emerging non-volatile memory devices has been widely explored recently. However, most realizations typically use 2T-2R synapses, resulting in sub-optimal area utilization. In this study, we investigate alternate computation mapping strategies to realize BNN using selectorless resistive random access memory arrays. A new differential computation scheme that shows a comparable performance with the well-established XNOR computation strategy is proposed. Through extensive experimental characterization, BNN implementation using a non-filamentary bipolar oxide-based random access memory device-based crossbar is demonstrated for two datasets: (i) experimental characterization was performed on a thermal-image based Rock-Paper-Scissors dataset to analyze the impact of sneak-paths with real-hardware experiments. (ii) Large-scale BNN simulations on the Fashion-MNIST dataset with multi-level cell characteristics of non-filamentary devices are performed to demonstrate the impact of device non-idealities.

Vertical N-Type and P-Type Nanosheet FETs With C-Shaped Channel

We presented and demonstrated both n- and p-type vertical C-shaped-channel nanosheet field-effect transistors (VCNFETs) featured with precise control of both channel thickness and gate length. The VCNFETs were fabricated by high-quality Si/SiGe epitaxy and atomic layer deposition to obtain nanometer-scale process control and self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gate (HKMG). The integration flow is compatible with the process used in the mainstream industry and it can be easily extended to vertically stacked devices. Both the gate length and the channel thickness of the VCNFETs are mainly determined by the thicknesses of Si/SiGe films grown by epitaxy, instead of lithography and etch techniques. Perfect subthreshold swing (SS), small drain-induced barrier lowering (DIBL), and large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio were achieved for both n- and p-VCNFETs due to the crystalline silicon channel and the well-defined doping profiles. The device performance and optimization were also investigated and discussed. Used as access transistors in dynamic random access memory (DRAM) array, VCNFETs were also demonstrated for the potential applications to 10-nm DRAM and beyond.

A Novel Cascadable TCAM Using RRAM and Current Race Scheme for High-Speed Energy-Efficient Applications

In this work, a novel ternary content addressable memory (TCAM) design is proposed using resistive random-access memory (RRAM) array in 2T2R configuration. The suggested memory array adopts the current-race (CR) sensing mechanism incorporated with a match-line (ML) booster in the sensing amplifier (SA) to improve energy efficiency, search speed and tolerance to RRAM switching variation. Several innovations are implemented to enhance the design further. For large TCAM arrays, match-line sensing amplifier (MLSA) direct cascading (DC) and an SR-latch cascading (SRC) schemes are proposed and compared in search speed, energy efficiency and MLSA noise margin. A same clock phase cascading (SCPC) scheme is also introduced to reduce latency in cascading structure by placing evaluation phase of all stages in the same clock phase. Furthermore, an RRAM-based tunable delay element (RRAM-TDE) is used in the TCAM design to provide flexibility and robustness against RRAM switching variation. The resulting system demonstrates excellent speed, energy and area efficiency against other TCAM designs using CMOS and emerging non-volatile memory (eNVM). To the best of our knowledge, the proposed 64-bit 1-stage TCAM system's speed and energy consumption match the best performance reported by other eNVM-based TCAM designs. The proposed design on a 128-bit 2-stage system also has speed and energy consumption comparable to SRAM-based TCAMs with the extra advantages of (a) compact size (90% reduction) and (b) non-volatility.

Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

AbstractA hole‐type vertical structure is adopted to fabricate a vertically stacked resistive switching random access memory (ReRAM) array. The vertical configuration is more advantageous in lowering the process cost and increasing integration density than the horizontal configuration. However, the memory cells constituting the hole‐type vertical‐ReRAM (V‐ReRAM) array can be short‐circuited if a middle electrode is introduced to stack a rectifying element onto the memory layer. Thus, a self‐rectifying Pt/Ta2O5/Al‐doped HfO2/TiN ReRAM is adopted in this study to prevent the sneak‐current and short‐circuit issues for efficient operation in vertical crossbar array configuration. A two‐ or three‐layer stacked V‐ReRAM is fabricated, and its electrical characteristics are evaluated. High switching uniformity and sufficiently large memory window and rectification ratio are acquired. The low operation power and high switching uniformity render this V‐ReRAM array suitable for high‐capacity storage devices. However, the on‐state data retention needs improvement. Detailed investigation of the three‐layer stacked device identifies that lateral charge spreading between neighboring cells in the V‐ReRAM causes such a problem, which can be mitigated by increasing the intercell distance.

Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks

The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time.

Improved rectification characteristics of the GR/Blue P/GR selector by doping: First-principles study

In this paper, a graphene (GR)/monolayer (ML) blue phosphorous (Blue P)/GR selector was studied based on the first-principles theory. Due to different contact edges, four GR–Blue P lateral heterojunctions were constructed, namely, armchair–armchair (A–A), zigzag–armchair (Z–A), armchair–zigzag (A–Z), and zigzag–zigzag (Z–Z). As demonstrated by the binding energy and Mulliken population, we found that the Z–Z heterojunction was relatively stable. Furthermore, a GR/Blue P/GR selector based on the Z–Z heterojunction interface was proposed with a nonlinear (NL) coefficient is 105. However, the drive current of this device was insufficient. A P atom of the resistive layer was separately substituted with four different atoms (Ni, Cu, N, and Cl) to effectively improve selector performance. The energy band structure was half-metallic when doped with Ni or Cu while the others still maintained semiconductor characteristics, and the bandgap was significantly reduced. The Schottky barrier height and width of the interface (GR–Blue P), with Cl as the substituted impurity, were the smallest, leading to a three order of magnitude increase in the NL coefficient. The calculation shows that GR/Blue P/GR devices can be integrated as selectors in Resistive switching Random Access Memory (RRAM) arrays. This work also has a certain guiding significance for manufacturing new types of two-dimensional lateral selector apparatuses.

In‐memory calculation with embedded arithmetic and logic units for deep neural network

The computation of multiplication in memory is a promising approach to reduce latency and improve the energy efficiency of intelligence edge processors. However, the multiplication operation in the analog domain is associated with complex peripheral circuits and low accuracy. In this letter, an static random-access memory (SRAM) array with embedded low area cost arithmetic and logic units is proposed, which realizes high-speed and high-precision multi-bit multiplication. The calculation delay is as low as 164 ps. The maximum integral non-linearity (INL) is only 0.340 least significant bit, which is 1/16 of that of analog domain multiplication.

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing

Frequent to-and-from data transfers in the von Neumann architecture limit the overall throughput. One of the promising approaches used to overcome von Neumann bottleneck is in-memory computing (IMC) that aims to embed computing in memory to reduce the transfer of memory-processor data. This study proposes a configurable 6-transistor (6T) static random access memory (SRAM) array with a multilevel shared structure for IMC. A multilevel shared structure can effectively improve the utilization rate of the module. In addition to the conventional SRAM operation, the configurable structure can also perform the sum of absolute differences (SAD) and Hamming distance (HD) calculations. To quickly identify the minimum value among multiple calculation results, a four-input sense amplifier (SA) is proposed. The performance of the proposed memory is simulated in a 65-nm CMOS process. The post-layout simulation results show good linearity of the multirow read in the SAD and HD modes. The mean time required by the four-input SA to obtain the result is 190 ps. The SAD and HD calculations yield consumptions of 67.44 fJ/byte and 0.64 fJ/bit, respectively, at 0.8 V. Furthermore, a single column-sharing comparator consumes 2.78 and 3.41 pJ at 0.8 V in the SAD and HD modes, respectively.

A Practical Design-Space Analysis of Compute-in-Memory With SRAM

Analog-domain compute-in-memory (CIM) is a technique that has emerged in part as a response to the memory-intensive vector-matrix-multiplications (VMMs) required to implement important emerging applications, notably machine learning inference. Implemented CIM systems have demonstrated good energy efficiency for lower-precision systems and/or with loosened compute-level accuracy requirements. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A priori</i> it is unclear exactly how the efficiency advantages of CIM emerge and therefore the generalizability of these advantages, beyond the specific demonstrated examples, is unclear. Noting that not all VMM-heavy workloads can tolerate imperfect accuracy and/or reduced precision, this work combines high-level models with circuit models and simulations to examine the efficiency gains and penalties associated with CIM in static random-access memory (SRAM) arrays. Extracted models which are needed to make assertive statements about CIM are developed and discussed. An energy comparison to standard SRAM is made, and the issues of accuracy loss and area are contextualized. Finally, a few example models comparing the energy efficiency of CIM to that of SRAM are shown to verify that CIM is most effective for error-tolerant, low-precision applications.

In-Memory Multibit Multiplication Based on Bitline Shifting

Artificial intelligence algorithms entail an enormous number of multiplication operations. If these operations are implemented within a static random-access memory array, the considerable data migration between the memory and processor can be avoided; hence, a substantial amount of energy and time can be saved. Therefore, in-memory multibit multiplication is an important method for improving energy efficiency. However, the results of in-memory calculations are expressed in the form of bitline voltage. For an increase in the number of operation bits, the voltage representing the least-significant bit (LSB) of the operation result must decrease. To overcome this problem, we propose a strategy that decomposes multibit multiplication into combinations of binary operations based on bitline shifting. The voltage differences can be stored at different corresponding capacitances instead of at one point. Therefore, the LSB voltage difference remains high when the number of supported bits increases; for example, when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\,\,4\,\, {{\times }}\,\,3$ </tex-math></inline-formula> bits are calculated simultaneously, the LSB of the multiplication-accumulation result can reach 10 mV. The proposed in-memory multibit multiplication is achieved at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {{\sim }}282$ </tex-math></inline-formula> MHz with 25.9 TOPS/W energy consumption.