Random Access Memory Array Research Articles

Data retention investigation in Al:HfO2-based resistive random access memory arrays by using high-temperature accelerated tests

In this work, the feasibility of using accelerated tests at high temperatures to assess the data retention on resistive random access memory devices was evaluated on Al:HfO2-based 1-transistor-1-resistor 4 kbit arrays. By annealing the samples at four different temperatures (190, 210, 230, and 260°C) for 10 h, different distributions of retention failure times were obtained and modeled by using Weibull distributions. Based on the temperature dependency of these distributions, the Arrhenius activation energy of the degradation process was calculated (1.09 eV). In addition, the maximum temperature that guarantees a retention time to failure of a 10 year lifetime was extrapolated (105°C).

NBTI-Related Variability Impact on 14-nm Node FinFET SRAM Performance and Static Power: Correlation to Time Zero Fluctuations

A Monte Carlo SPICE framework is proposed to evaluate the impact of negative bias temperature instability (NBTI) variability on performance and static power ( ${P}_{\text {S}}$ ) of static random access memory (SRAM) array on 14-nm node FinFETs. Gamma distribution is found to be applicable for NBTI-induced threshold voltage ( $\Delta {V}_{T}$ ) and subthreshold slope ( $\Delta $ SS) shifts by using data set from different sources. A compact variability model is proposed for the time evolution of mean and variance of NBTI distribution, considering any possible correlation between time zero and NBTI variability. The relative sensitivity of device and SRAM degradation are evaluated, by correlating SRAM static noise margin degradation to transistor level ${V}_{T}$ shift. The impact of $\Delta $ SS on ${P}_{\text {S}}$ improvement due to NBTI is also evaluated.

Rectifying Resistive Memory Devices as Dynamic Complementary Artificial Synapses.

Brain inspired computing is a pioneering computational method gaining momentum in recent years. Within this scheme, artificial neural networks are implemented using two main approaches: software algorithms and designated hardware architectures. However, while software implementations show remarkable results (at high-energy costs), hardware based ones, specifically resistive random access memory (RRAM) arrays that consume little power and hold a potential for enormous densities, are somewhat lagging. One of the reasons may be related to the limited excitatory operation mode of RRAMs in these arrays as adjustable passive elements. An interesting type of RRAM was demonstrated recently for having alternating (dynamic switching) current rectification properties that may be used for complementary operation much like CMOS transistors. Such artificial synaptic devices may be switched dynamically between excitatory and inhibitory modes to allow doubling of the array density and significantly reducing the peripheral circuit complexity.

Exploring a SOT-MRAM Based In-Memory Computing for Data Processing

In this paper, we propose a Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) array design that can simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic operation without add-on logic circuits. The computed output can be simply read out like a typical MRAM bit-cell through the modified peripheral circuit. Such intrinsic in-memory computation can be used to process data locally and transfer the “cooked” data to the primary processing unit (i.e., CPU or GPU) for complex computations with high precision requirement. It greatly reduces the power-hungry and long-distance data communication, and further leads to extreme parallel computation within memory. In this work, we further propose an in-memory edge extraction algorithm as a case study to demonstrate the efficiency of the in-memory pre-processing methodology. The simulation results show that our edge extraction method reduces data communication as much as 8x for grayscale image, thus greatly reducing system energy consumption. Meanwhile, the F-measure result shows only <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 10 percent degradation compared to conventional edge detection operator, such as Prewitt, Sobel, and Roberts. Moreover, the edges extracted from the memory show comparable good quality with Canny edges in the context of edge-based motion detection and cross-modality object recognition.

Unveiling the Switching Mechanism of a TaO&lt;italic&gt;x&lt;/italic&gt;/HfO2 Self-Selective Cell by Probing the Trap Profiles With RTN Measurements

Self-selectivecells (SSCs) with built-in nonlinearity provide a promising solution for overcoming the leakage current issue of 3-D vertical resistive random access memory arrays. However, deep understanding of the switching mechanism of the SSC device is still lacking, hindering the effective improvement of the device performance. In this letter, we investigated the switching mechanism of the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC device by probing the trap profiles with RTN measurements. Both the vertical locations and energy levels (X <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of defects in the HRS and LRS could be calculated by the bias-dependence of the capture and emission time constants (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> and τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ). Using the comparison of the defect profiles before and after the resistive switching, an active region in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer adjacent to the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer could be clearly identified. Based on these results, a clear picture of resistive switching in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC was obtained.

IMFlexCom

In this article, we propose an &lt;u&gt;I&lt;/u&gt;n-&lt;u&gt;M&lt;/u&gt;emory &lt;u&gt;Flex&lt;/u&gt;ible &lt;u&gt;Com&lt;/u&gt;puting platform (IMFlexCom) using a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array architecture, which could work in dual mode: memory mode and computing mode. Such intrinsic in-memory logic (AND/OR/XOR) could be used to process data within memory to greatly reduce power-hungry and long distance massive data communication in conventional Von Neumann computing systems. A comprehensive reliability analysis is performed, which confirms ∼90mV and ∼10mV (worst-case) sense margin for memory and in-memory logic operation in variations on resistance-area product and tunnel magnetoresistance. We further show that sense margin for in-memory logic computation can be significantly increased by increasing the oxide thickness. Furthermore, we employ bulk bitwise vector operation and data encryption engine as case studies to investigate the performance of our proposed design. IMFlexCom shows ∼35× energy saving and ∼18× speedup for bulk bitwise in-memory vector AND/OR operation compared to DRAM-based in-memory logic. Again, IMFlexCom can achieve 77.27% and 85.4% lower energy consumption compared to CMOS-ASIC- and CMOL-based Advanced Encryption Standard (AES) implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation with 66.7% less area overhead.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.

Sub-1-V–60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Internal filament modulation in low-dielectric gap design for built-in selector-less resistive switching memory application

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfOx/SiOx-based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfOx/SiOx structure. The stacking HfOx/SiOx-based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO2/Al2O3/TiOx (HAT) RRAM

AbstractComplementary resistive switching (CRS) is a suitable approach to minimize the sneak leakage paths through a large resistive random access memory (RRAM) array. Here, an effective CRS design with a HfO2/Al2O3/TiOx (HAT) trilayer structure integrated in a 3D vertically stacked RRAM array is reported. The design shows voltage‐controlled resistive switching and CRS performance with multilevel operations. High‐speed switching is observed with the HAT design. The device shows SET and the RESET transitions with speeds of −3.5 V@30 ns and +3.8 V@150 ns, respectively. As well as with the DC measurements, the CRS switching is achieved under AC switching dynamics measurement. Maintaining the same applied pulse polarity, the lower amplitude can switch the device to the SET and the higher amplitude can switch it to the RESET. A highly nonlinear (nonlinearity &gt;102) CRS is obtained at a high temperature of 150 °C. In the HAT devices, the origin of CRS is due to the anionic redistribution in HfO2 and TiOx layers, leaving Al2O3 as tunnel barrier. The achievements reported here indicate the applicability of the HAT design for future high‐speed high‐density applications.

Novel Computing Method for Short Programming Time and Low Energy Consumption in HfO2 Based RRAM Arrays

This paper proposes a novel technique for reducing programming time and energy consumption in resistive random access memory (RRAM) arrays based on ramped voltage stress (RVS). RVS method is correlated to conventional constant voltage stress method (CVS) using an analytical model validating RVS as a reliable technique for switching time characterization in RRAM arrays. RVS method is optimized to reduce programming time and energy consumption providing a quantitative and qualitative link between programming method and tails improvement in memory arrays. Switching time distribution is much more controlled: half a decade using optimized RVS in comparison with ~3 decades distribution using conventional CVS method. Energy consumption is reduced by 4 orders of magnitude at $+5\sigma $ quantiles using our proposed technique compared to CVS.

Designing a 2-to-4 decoder on nanoscale based on quantum-dot cellular automata for energy dissipation improving

Quantum dot Cellular Automata (QCA) as a new architecture at the nanoscale is developed as a feasible alternative for the existing Complementary Metal–Oxide–Semiconductor (CMOS) designs. The decoder in the QCA is a very important circuit to address the QCA-based random access memory arrays. It plays a key role in many circuit designs, such as Controlled Logic Block (CLB), Field Programmable Gate Array (FPGA), and memory circuits’ designs. In this paper, a five-input majority gate is used in a modular design methodology to design a 2-to-4 decoder in QCA. The proposed 2-to-4 QCA-based decoder can be utilized to synthesize n-to-2n decoders as well. The functional correctness of the proposed circuit is evaluated using QCADesigner tool. Also, QCAPro simulator as a popular power estimator tool in QCA evaluates the power dissipation. The obtained results have shown the significant success in terms of clock speed (%57), wire-crossing (%33), cell number (%27), area (%26) and power dissipation than the existing designs.

Built-In Nonlinear Characteristics of Low Power Operating One-Resistor Selector-Less RRAM by Stacking Engineering

The sneak-path leakage current issue is one of the severe hindrances for the application of high density resistive random access memory (RRAM) array design. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of HfOx/SiOx-based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing internal filament location with low effective dielectric constant intending in HfOx/SiOx structure. The stacking HfOx/SiOx-based RRAM device as the one-resistor-only memory cell is applicable without additional selector device to solve the sneak-path issue with switching voltage ~1 V, which is desirable for low power operating in built-in nonlinearity crossbar array configuration.

A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs

The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a $256\times256$ STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases.

3D Cross-Point Spin Transfer Torque Magnetic Random Access Memory

We explore a 3D cross-point spin transfer torque magnetic random access memory (STT-MRAM) array based on the integration of a perpendicular magnetic tunneling junction (pMTJ) with a matching two-terminal selector. The integrated two-terminal device provides a unique opportunity for a high density, low cost stackable storage class memory that can achieve a fast operation speed, long data retention, low bit error rate (BER) and high endurance. 55[Formula: see text]nm size pillar shaped pMTJ and selector devices have been fabricated and characterized. The selector is compatible with pMTJ whether it is in the high or low resistance state. The pMTJ can be RESET and SET after the selector turns on. We model the dynamic switching of the coupled pMTJ and selector devices. Our model shows the importance of the optimal matching of pMTJ magnetic properties with selector resistive properties to achieve high performance.

Array Termination Impacts in Advanced SRAM

An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and $V_{\min }$ fail count, are examined using a 14-nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

In this paper, we study the 1-selector1-resistor (1S1R) cross-point resistive random access memory (ReRAM) array because of its high density, fast access time, and ultralow stand-by power. Specifically, we focus on an access scheme where a data line is parallelly accessed from multiple subarrays with multibits accessed per subarray. A direct implementation of such a scheme has high energy efficiency but lower reliability compared with a single bit per subarray baseline scheme. So this paper proposes a low cost multilayer approach to improve energy-efficiency of multibits per access scheme without compromising reliability. At the cell level, we show how proper choices of bit-line and source-line voltage and SET recovery help reduce error rate by ten times. At the system level, we propose a new rotated multiarray access scheme where the average error rate of every accessed data line is one order of magnitude lower than the worst case, making it possible to achieve block failure rate of 10-10 with a simple Bose, Chaudhuri, and Hocquenghem t = 4 code. We show that for a 1 GB 1S1R ReRAM, the proposed approach can reduce energy by 41% with 2% extra area while maintaining latency and reliability compared with the baseline system.

Flexible resistive random access memory devices by using NiOx/GaN microdisk arrays fabricated on graphene films

We report flexible resistive random access memory (ReRAM) arrays fabricated by using NiOx/GaN microdisk arrays on graphene films. The ReRAM device was created from discrete GaN microdisk arrays grown on graphene films produced by chemical vapor deposition, followed by deposition of NiOx thin layers and Au metal contacts. The microdisk ReRAM arrays were transferred to flexible plastic substrates by a simple lift-off technique. The electrical and memory characteristics of the ReRAM devices were investigated under bending conditions. Resistive switching characteristics, including cumulative probability, endurance, and retention, were measured. After 1000 bending repetitions, no significant change in the device characteristics was observed. The flexible ReRAM devices, constructed by using only inorganic materials, operated reliably at temperatures as high as 180 °C.

Parallel programmable nonvolatile memory using ordinary static random access memory cells

A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 µm technology.