Ramp Bias Research Articles

A Fast Response PWM Buck Converter With Active Ramp Tracking Control in a Load Transient Period

This brief proposes a pulse-width modulation buck converter with an active ramp tracking control to achieve a fast load transient response. When the difference between the output voltage and reference voltage is increased to a certain level in the load transient situation, the ramp bias voltages track the error voltage and provide a full duty to power switches. This helps restore the output voltage to the reference voltage, improving the load transient response speed and decreasing the overshoot/undershoot and their recovery times at the output voltage. A test chip was fabricated in a 65-nm CMOS technology, whose performance evaluation results indicated that the proposed buck converter reduced overshoot/undershoot at the output by up to 61.1% and the recovery time by up to 60.0% for a 450-mA load current step. The maximum power conversion efficiency of the proposed converter is 92.0% for 3.3 V input voltage and 1.8 V output voltage.

Low Power Microwave Signal Detection With a Spin-Torque Nano-Oscillator in the Active Self-Oscillating Regime

A spin-torque nano-oscillator (STNO) driven by a ramped bias current can perform spectrum analysis quickly over a wide frequency bandwidth. The STNO spectrum analyzer operates by injection locking to external microwave signals and produces an output DC voltage $V_{\rm dc}$ that temporally encodes the input spectrum. We found, via numerical analysis with a macrospin approximation, that an STNO is able to scan a $10~\rm GHz$ bandwidth in less than $100~\rm ns$ (scanning rate $R$ exceeds $100~\rm MHz/ns$). In contrast to conventional quadratic microwave detectors, the output voltage of the STNO analyzer is proportional to the amplitude of the input microwave signal $I_{\rm rf}$ with sensitivity $S = dV_{\rm dc}/dI_{\rm rf} \approx 750~\rm mV/mA$. The minimum detectable signal of the analyzer depends on the scanning rate $R$ and, at low $R \approx 1~\rm MHz/ns$, is about $1~\rm pW$.

Experimental quantum-walk revival with a time-dependent coin.

We demonstrate a quantum walk with time-dependent coin bias. With this technique we realize an experimental single-photon one-dimensional quantum walk with a linearly ramped time-dependent coin flip operation and thereby demonstrate two periodic revivals of the walker distribution. In our beam-displacer interferometer, the walk corresponds to movement between discretely separated transverse modes of the field serving as lattice sites, and the time-dependent coin flip is effected by implementing a different angle between the optical axis of half-wave plate and the light propagation at each step. Each of the quantum-walk steps required to realize a revival comprises two sequential orthogonal coin-flip operators, with one coin having constant bias and the other coin having a time-dependent ramped coin bias, followed by a conditional translation of the walker.

Revisiting plasma hysteresis with an electronically compensated Langmuir probe

The measurement of electron temperature in plasma by Langmuir probes, using ramped bias voltage, is seriously affected by the capacitive current of capacitance of the cable between the probe tip and data acquisition system. In earlier works a dummy cable was used to balance the capacitive currents. Under these conditions, the measured capacitive current was kept less than a few mA. Such probes are suitable for measurements in plasma where measured ion saturation current is of the order of hundreds of mA. This paper reports that controlled balancing of capacitive current can be minimized to less than 20 μA, allowing plasma measurements to be done with ion saturation current of the order of hundreds of μA. The electron temperature measurement made by using probe compensation technique becomes independent of sweep frequency. A correction of ≤45% is observed in measured electron temperature values when compared with uncompensated probe. This also enhances accuracy in the measurement of fluctuation in electron temperature as δT(pk-pk) changes by ~30%. The developed technique with swept rate ≤100 kHz is found accurate enough to measure both the electron temperature and its fluctuating counterpart. This shows its usefulness in measuring accurately the temperature fluctuations because of electron temperature gradient in large volume plasma device plasma with frequency ordering ≤50 kHz.

Photoelectrochemical Etching and Removal of the Irregular Top Layer Formed on InP Porous Nanostructures

A photoelectrochemical (PEC) process was developed to remove the irregular top layer from InP porous nanostructures. After anodic formation of a nanopore array, the PEC process repeated in the same electrolyte under illumination. The etching rate of the pore surfaces was strongly associated with their structural properties, being greater in the irregular top layer. The irregular top layer was completely removed by monitoring and controlling the anodic photocurrents in the ramped bias mode.

Unfolding and Extraction of a Transmembrane α-Helical Peptide: Dynamic Force Spectroscopy and Molecular Dynamics Simulations

An atomic force microscope (AFM) was used to visualize CWALP1923 peptides (+H3N-ACAGAWWLALALALALALALWWA-COO−) inserted in gel-phase DPPC and DSPC bilayers. The peptides assemble in stable linear structures and domains. A model for the organization of the peptides is given from AFM images and a 20ns molecular dynamics (MD) simulation. Gold-coated AFM cantilevers were used to extract single peptides from the bilayer through covalent bonding to the cystein residue. Experimental and simulated force curves show two distinct force maxima. In the simulations these two maxima correspond to the extraction of the two pairs of tryptophan residues from the membrane. Unfolding of the peptide precedes extraction of the second distal set of tryptophans. To probe the energies involved, AFM force curves were obtained from 10 to 104nm/s and MD force curves were simulated with 108–1011nm/s pulling velocities (V). The velocity relationship with the force, F, was fitted to two fluctuation adhesive potential models. The first assumes the pulling produces a constant bias in the potential and predicts an F∼ln (V) relationship. The second takes into account the ramped bias that the linker feels as it is being driven out of the adhesion complex and scales as F∼(ln V)2/3.

Growth Control of Carbon Nanotube using Various Applied Electric Fields for Electronic Device Applications

The control of the growth direction of a carbon nanotube was accomplished by applying an electric field during the growth of the carbon nanotube. The effects of two types of applied bias, one is a constant DC bias, and the other is a ramp bias, on the control of the growth direction were examined. By maintaining a constant DC bias we could control the growth direction of the carbon nanotube, however, the bridging ratio between the two electrodes was as small as 35%. We suppose that this low bridging ratio may be caused by the etching effect of hydrogen. When a ramp bias was applied, bridging ratio tended to increase with the slope of ramp bias. Under optimal conditions, the bridging ratio reached a value as high as 95%.

High-speed measurement method of quantized energy levels in Josephson junctions using SFQ circuits

A single flux quantum (SFQ) circuit has been designed to demonstrate an energy levels quantization in a Josephson Junction. The high-speed operation of SFQ circuits realizes applying a high-speed ramped bias current to a Josephson junction, which allows the noiseless experiment at higher temperature. A high-speed ramped bias current (d I/d t=2000 A/s) is applied to a Josephson junction using the proposed circuit. Although the energy levels quantization has not been observed yet, the obtained escape rate was high enough to observe the energy levels quantization. The proposed circuit indicates the effectiveness of SFQ circuits as experimental apparatuses.

A New RMSP Reset Pulse for Improved Reset Discharge Controllability in AC PDP

We are proposing a new ramp-biased multiple short pulse (RMSP) for AC plasma-display panels, which is composed of multiple short pulses with fast ramp bias up to 5 V//spl mu/s. Through adjustment of the period and duty ratio of RMSP and using the tail effect, we have succeeded in controlling the final wall voltage level by /spl plusmn/10 V from the level of (peak RMSP voltage)-(discharge breakdown voltage). We applied RMSP to the reset period and achieved stable discharge, higher address margin, and lower background luminance as well as shorter reset time. When compared with the conventional ramp reset method, the new reset method using RMSP could improve the darkroom contrast ratio by 52% and shorten the reset time by 215 /spl mu/s for each subfield.

P‐58: A New Reset Method Using Ramp biased Multiple Short Pulses RMSP for AC PDP

AbstractWe are proposing a new reset method for AC PDP, which is composed of multiple short pulses with fast ramp bias voltage. We have succeeded in achieving low background luminance as well as stable and higher address margin. When compared with the conventional ramp reset method, the darkroom contrast ratio can be increased by 52% and the reset time can be shortened by 215μs for each subfield.

Analysis of an experimental technique for determining Van der Pol parameters of a transistor oscillator

The Van der Pol (VDP) model of a transistor oscillator describes the behaviour of the oscillator with three parameters. When operating in steady state, only two parameters can be determined by spectrum analysis, these being the oscillation frequency and amplitude of oscillation. In this paper, a technique for measuring the other VDP parameter is examined. In this approach, a periodically modulated voltage is added to the bias of the oscillator to perturb the operational state. A theoretical derivation shows that the power spectrum of the perturbed oscillator contains additional information for determination of the other VDP parameter. A simple analytical perturbation formula predicts the oscillator's response to the ramped bias. Our experimental results agree with the analytical perturbation solution and therefore, this allows one to read off the other VDP parameter from the experimental data. The VDP model allows one to predict the behaviour of coupled transistor oscillators more accurately and simply than does the traditional large-signal model of the transistor. This VDP model will simplify oscillator array design since the number of parameters needed to describe each oscillator is reduced from that which would be required using a large-signal circuit model.

Field-enhanced nonequilibrium C/V and I/V characteristics of MOS capacitor under linear voltage ramp bias

A theoretical method is presented to analytically describe nonequilibrium C/V and I/V characteristics of an MOS capacitor under linear voltage ramp bias. Unlike previous theories the carrier emission probability is assumed to be field-dependent and therefore the transients are known as field enhanced. The one-dimensional Poole–Frenkel model is used to describe the carrier-emission probability dependent on the applied electric field. It has been verified that this model is available for coulombic centres. A differential equation is established to describe the change of the space-charge region width with time. The MOS capacitance and gate current are related to the space-charge region width. In this way the field enhanced nonequilibrium C/V and I/V characteristics are obtained.

Description of non-equilibrium phenomena in MIS device under linear voltage ramp bias

A new theoretical method to describe the non-equilibrium characteristics of a metal-insulator-semiconductor (MIS) device under a linear voltage ramp bias is presented. Unlike previous theoretical analyses the effect of time-dependent carrier generation of bulk traps on these characteristics has been considered and an improved model for generation width has been applied. A differential equation is formed to describe the change of depletion region width with time during transients. The high frequency MIS capacitance and gate current are related to depletion region width. In this way the non-equilibrium capacitance-voltage ( C− V) and current-voltage ( I− V) characteristics can be described.

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.

Defect levels in electrodeposited n-type CdTe thin films

Admittance spectroscopy is used to measure electron traps near the conduction band of the n-type electrodeposited CdTe thin films. Several samples of Ni-CdTe Schottky-barrier and Ni-TeO2-CdTe devices are used in the measurement. Two donor levels with activation energies around 0.12 eV and between 0.19 and 0.26 eV are detected. In addition, there may be one or more shallow donor levels within 0.04 eV from the conduction band. Capacitance loops are observed in the capacitance-voltage measurements performed at different temperatures and bias sweep rates. The activation energies, densities, and electron-capture cross sections of the two slow electron-trap levels responding to the cyclical ramp bias are estimated. The rise and decay photocapacitance transient measurements at 295 K reveal two electron-trap levels with photoionization threshold energies of 0.8 and 1.3 eV. These two levels are suspected to correspond to the other two slow electron-trap levels estimated in the capacitance-voltage measurement and located around or above the midgap. The differences between thermal and optical ionization energies and the slow electron-capture rates of these two levels may be explained by the nonradiative, thermally activated capture processes with large lattice relaxation. Numerous defects around and below the midgap are detected by the steady-state photocapacitance measurement at 100 K. A band of seven defect levels spreading within 0.6 to 1.0 eV is observed. Large capacitance changes are recorded at 1.37, 1.41, and 1.45 eV. These three levels are speculated to be the major compensating acceptor levels. Based on both the photocurrent and photocapacitance measurements, electrons emitted from the 1.02-, 1.06-, 1.21-, and 1.28-eV levels are believed to arise from the defects at the TeO2-CdTe interface.

Theory of non-equilibrium phenomena in an MIS device under linear voltage ramp bias

A theoretical investigation into the non-equilibrium characteristics displayed by a metal-insulator-semiconductor (MIS) device when subjected to a linear voltage ramp is presented. Unlike previous theoretical analyses a time varying bulk trap generation rate is considered. It is shown that the current-voltage characteristics obtained by including this time dependence are the same as those obtained by assuming the bulk traps generate instantly at their steady-state value. Two different starting conditions are considered, namely, accumulation or depletion and strong inversion. The problem associated with commencing the sweep in accumulation or depletion when the concern is only with bulk properties is one of interface trap emission and generation and the effect these may have on the resulting I– V characteristic. This is overcome by initially biasing the device into strong inversion. For this condition bulk trap generation actually takes place right up to the semiconductor surface even though those traps near the surface have an initial occupancy of zero.

Improved model for nonequilibrium phenomena in MIS device under linear voltage ramp bias

An improved theoretical investigation into the nonequilibrium characteristics displayed by a metal-insulator-semiconductor device when subjected to a linear voltage ramp is presented. The model takes into account the finite bulk-trap generation width for those traps initially above the Fermi-level. The resulting I/V characteristics show considerable deviation from those where it assumed that the bulk traps intially above the Fermi-level either generate as a whole or do not generate at all.

Thermal and nonthermal switching in a-CdAs2 thin-film sandwich structures: The effect of bias rate

Thin-film devices incorporating a-CdAs2 which display current-controlled negative differential resistance (CNDR) under quasistatic bias conditions are described. By biasing devices with short rapid rise-time pulses, threshold switching is observed to set in at much higher voltages than needed for quasistatic CNDR. The transition region between these extremes has been studied by biasing the devices with an adjustable power ramp whose slope was varied over many orders of magnitude. Under ramp bias, the devices show CNDR with a turnover voltage approaching the quasistatic value for bias times to turnover of 0.1 sec or longer. More rapid bias rates result in CNDR with a strongly increasing turnover voltage with increasing bias rate. Analysis of the temperature of the device during ramp bias indicates that the turnover mechanism is Joule-heat induced for bias times of 0.5 sec or longer, ’’electronic’’ for bias times of 10−3 sec or less, and of mixed origin in between.