Abstract
A new theoretical method to describe the non-equilibrium characteristics of a metal-insulator-semiconductor (MIS) device under a linear voltage ramp bias is presented. Unlike previous theoretical analyses the effect of time-dependent carrier generation of bulk traps on these characteristics has been considered and an improved model for generation width has been applied. A differential equation is formed to describe the change of depletion region width with time during transients. The high frequency MIS capacitance and gate current are related to depletion region width. In this way the non-equilibrium capacitance-voltage ( C− V) and current-voltage ( I− V) characteristics can be described.
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