Improved model for nonequilibrium phenomena in MIS device under linear voltage ramp bias

Abstract

An improved theoretical investigation into the nonequilibrium characteristics displayed by a metal-insulator-semiconductor device when subjected to a linear voltage ramp is presented. The model takes into account the finite bulk-trap generation width for those traps initially above the Fermi-level. The resulting I/V characteristics show considerable deviation from those where it assumed that the bulk traps intially above the Fermi-level either generate as a whole or do not generate at all.