General experimental method of parameter extraction for CMOS timing macromodels

Abstract

A new general experimental method for timing macromodel parameter extraction is proposed and investigated. Based on the general timing models developed and the measured timing data of CMOS inverters, the critical field exponent UEXP of carrier mobilities in transient operation, the optimal gate/source voltage and pn-junction voltage, and the capacitances associated with a logic gate are extracted by using the proposed method. It is shown that the extracted value of UEXP is twice the conventional value owing to the integration effect on the drain currents in delay calculations. The optimal linearisation gate/source voltage is about 0.7 VDD, whereas the pn-junction voltage is approximately VDD/2. By using the extracted timing parameters, the accuracy of the timing macromodels developed is improved and experimentally verified. The possibility of accuracy improvement and experimental verification makes the proposed method quite helpful in developing efficient timing macromodels for digital VLSI.