Theory of non-equilibrium phenomena in an MIS device under linear voltage ramp bias

Abstract

A theoretical investigation into the non-equilibrium characteristics displayed by a metal-insulator-semiconductor (MIS) device when subjected to a linear voltage ramp is presented. Unlike previous theoretical analyses a time varying bulk trap generation rate is considered. It is shown that the current-voltage characteristics obtained by including this time dependence are the same as those obtained by assuming the bulk traps generate instantly at their steady-state value. Two different starting conditions are considered, namely, accumulation or depletion and strong inversion. The problem associated with commencing the sweep in accumulation or depletion when the concern is only with bulk properties is one of interface trap emission and generation and the effect these may have on the resulting I– V characteristic. This is overcome by initially biasing the device into strong inversion. For this condition bulk trap generation actually takes place right up to the semiconductor surface even though those traps near the surface have an initial occupancy of zero.