Quaternary Logic Research Articles

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Multi-valued logic (MVL) extends binary logic by providing a framework to represent complex systems with more than two truth values. MVL was introduced to confront the enormous interconnect issue associated with the binary logic in implementing the presnt day complex nanoelectronic architectures. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFETs), combined with the ability of resistive random-access memory (RRAM) to store multiple resistance values, has enabled the design of quaternary logic gates and arithmetic circuits. A new CNTFET-based design architecture has been proposed to implement the quaternary logic compatible with the existing technologies. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration. The static power reduction due to the effecciency of the design architecture and high OFF state resistance offered by integrating RRAM into the logic design was explored.The proposed circuits have been subject to various types of parameter variations to validate thir proper functionality in presence of these variations.

High-Performance Photoinduced Tunneling Self-Driven Photodetector for Polarized Imaging and Polarization-Coded Optical Communication based on Broken-Gap ReSe2/SnSe2 van der Waals Heterojunction.

Novel 2D materials with low-symmetry structures exhibit great potential applications in developing monolithic polarization-sensitive photodetectors with small volume. However, owing to the fact that at least half of them presented a small anisotropic factor of ≈2, comprehensive performance of present polarization-sensitive photodetectors based on 2D materials is still lower than the practical application requirements. Herein, a self-driven photodetector with high polarization sensitivity using a broken-gap ReSe2/SnSe2 van der Waals heterojunction (vdWH) is demonstrated. Anisotropic ratio of the photocurrent (Imax/Imin) could reach 12.26 (635nm, 179mWcm-2). Furthermore, after a facile combination of the ReSe2/SnSe2 device with multilayer graphene (MLG), Imax/Imin of the MLG/ReSe2/SnSe2 can be further increased up to13.27, which is 4 times more than that of pristine ReSe2 photodetector (3.1) and other 2D material photodetectors even at a bias voltage. Additionally, benefitting from the synergistic effect of unilateral depletion and photoinduced tunneling mechanism, the MLG/ReSe2/SnSe2 device exhibits a fast response speed (752/928µs) and an ultrahigh light on/off ratio (105). More importantly, MLG/ReSe2/SnSe2 device exhibits excellent potential applications in polarized imaging and polarization-coded optical communication with quaternary logic state without any power supply. This work provides a novel feasible avenue for constructing next-generation smart polarization-sensitive photodetector with low energy consumption.

Charge transfer mechanism for realization of double negative differential transconductance

With development of information age, multi-valued logic (MVL) technology utilizing negative differential transconductance (NDT) phenomenon has drawn attention as next-generation computing technology that can replace binary logic. However, because conventional NDT devices primarily use ternary logic, multiple-peak NDT device is required for higher-radix MVL that can process more datasets. Here, van der Waals double-peak anti-ambipolar transistor (AAT) as NDT device was developed by utilizing peak voltage (Vpeak) modulation of NDT peak. For realization of quaternary logic, Vpeak modulation technology was developed through charge transfer mechanism from channel, thereby shifting NDT peak and increasing peak-to-valley current ratio (PVCR). Furthermore, Double-peak AAT was implemented through parallel configuration of two AATs with different Vpeak values. Finally, quaternary inverter with four widely stable logic states was implemented by utilizing the developed double-peak AAT with two distinct NDT peaks and high PVCR. This double-peak AAT is expected to contribute to the development of next-generation MVL technology capable of processing datasets.

Towards Nonvolatile Spintronic Quaternary Flip-Flop and Register Design

The exciting properties of multi-valued logic (MVL) in overcoming the limitations of binary systems have led to widespread research on this topic. Considering various types of MVL, quaternary logic is more compatible with the existing binary systems. This paper proposes a nonvolatile quaternary flip-flop (NQFF) based on the unique features of the carbon nanotube field-effect transistors (CNTFETs) and magnetic tunnel junctions (MTJs). The proposed NQFF utilizes Spin-Hall effect (SHE)-assisted spin-transfer torque (STT) MTJs to provide nonvolatility with lower write energy, and multi-Vt gate-all-around (GAA) CNTFETs offer higher performance. On the other side, due to the usage of a shadow latch and the design of the proposed circuit, the delay of MTJ switching does not affect the delay of the whole circuit. The simulation results show that the proposed NQFF offers 50% lower PDP when the system is idle for only 25% of its total operational time.

High performance quaternary logic designs using GNFETs

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.

Novel design of power-efficient quaternary logic gates using CNTFET

ABSTRACT This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.

QQCAsim: a new simulation tool for quaternary logic in QCA technology

QQCAsim: a new simulation tool for quaternary logic in QCA technology

Antiambipolar Transistor with Double Negative Differential Transconductances for Organic Quaternary Logic Circuits

AbstractOrganic integrated circuits have emerged as potential candidates for next‐generation computing technology because of their low‐cost production, light weight, and mechanical flexibility. However, the incompatibility of organic devices with modern lithographic techniques leads to a major bottleneck, that is, low integration density. Herein, it is attempted to solve this issue by developing an organic quaternary inverter that exhibits four distinguishable logic states and thus, can significantly improve the level of device integration. The key component of the inverter is a double‐peaked antiambipolar transistor (DAAT) with a double sequential negative differential transconductance characteristic. First, the DAAT is developed by employing two lateral p‐n heterojunctions, namely C8‐BTBT/PTCDI‐C8 and C8‐BTBT/PhC2‐BQQDI, in which three distinct conducting paths are produced in a step‐by‐step manner in accordance with the increase in the gate voltage (VG). Next, the quaternary inverter circuit is implemented by connecting the DAAT with an n‐type transistor. The inverter exhibits four logic states with a complete drain voltage to ground voltage sweep. Finally, a strategy of optimizing the thickness of the PTCDI‐C8 layer to improve the voltage transfer characteristics of the quaternary inverters is demonstrated. This study, thus, represents a step toward the development of high‐performance organic integrated circuits.

All-Optical Quaternary Logic Circuits with Bacteriorhodopsin Coated Microcavities

All-Optical Quaternary Logic Circuits with Bacteriorhodopsin Coated Microcavities

Quaternary Logic Circuits Based on Low-Voltage Programmable/Erasable Four-Level Organic Transistor Nonvolatile Memories

Developing the multi-valued logic circuits, that can handle more data than the conventional binary logic circuits, is a promising strategy to break through the well-known Moore’s law. In this letter, we demonstrate quaternary logic circuits, for the first time, based on the four-level organic thin-film transistor nonvolatile memories (OTFT-NVMs) as the core components. High-performance four-level OTFT-NVMs are achieved, with the low programming/erasing voltages of ±15 V, high mobility up to 7.4 cm2/Vs, reliable endurance, and stable retention capabilities. By connecting the four-level OTFT-NVMs with a load resistance in the reasonable ways, we build the logic circuits to reliably perform quaternary logic operations of NOT, NAND and NOR, respectively. Our works lay the foundation to develop the novel quaternary integrated circuits in hardware.

A New Quaternary Full Adder Cell based on CNFET for Use in Fast Arithmetic Circuits

Multi-valued logic potentially increases the efficiency of arithmetic circuits and digital signal processing. Quaternary logic can be suggested as a solution to the problem of power consumption and connection complexity in binary digital systems. The possibility of having several threshold voltage levels using the Carbon Nanotube Field Effect Transistor (CNFET) results in the widespread use of this technology in the design of multi-valued circuits. In this paper, a quaternary full adder cell has been proposed. The main goal of the proposed circuit is to reduce the critical delay path in the quaternary full adder circuit using a parallel design. The proposed circuit is compared with four quaternary full adders based on simulation results using HSPICE in 32 nm technology. The experimental results show the higher performance of the proposed quaternary full adder cell than the state-of-the-art designs.

Efficient and Highly Reliable Spintronic Non-volatile Quaternary Memory Based on Carbon Nanotube FETs and Multi-TMR MTJs

Due to the limitations of traditional binary circuits, such as high power consumption and large area and interconnections density, multi-valued logic (MVL) was offered as a solution. Quaternary logic is a form of MVL that is highly compatible with binary systems. This paper proposes a low-cost and highly reliable non-volatile quaternary memory benefiting from the adjustable threshold voltage property of gate-all-around carbon nanotube field-effect transistors (GAA-CNTFET) and non-volatile nature of magnetic tunnel junctions (MTJ). The proposed quaternary memory occupies less area and consumes lower power. The simulation results show that the proposed design offers up to 53%, 41%, and 69% lower average power, static power, and write power. Moreover, it offers up to 47% and 34% lower read power delay product (PDP) and write PDP, respectively. The proposed latch also occupies up to 23% lower area than the state-of-the-art non-volatile quaternary memories.

Emergence of multiple negative differential transconductance from a WSe2 double lateral homojunction platform

Recent advances in two-dimensional (2D) van der Waals heterostructures have re-spurred the investigation of non-linear negative differential carrier transport transistors as a potential ingredient for the upcoming digital-driven hyperconnected era. Although notable findings employing various 2D heterojunctions have been recently demonstrated, the performance metrics are insufficient to fulfill requirements for practical device applications, and fundamental difficulties associated with multiple vertical stacking processes in device fabrication must be resolved. Here, we report the realization of multiple negative differential transconductance (NDT) and resistance (NDR) characteristics obtained from a single p-i-n WSe2 double lateral homojunction (DLHJ) transistor. Forming the DLHJ through the selective surface charge transfer doping of a homogeneous bilayer WSe2 film, double NDT characteristics that excel those expected from individual junction components and have high peak-to-valley current ratios (PVCRs) of 36.6 and 12.9 are achieved. Performing combined experimental characterizations and first-principle calculations, obtained exceptional NDT performance at room temperature is determined to originate from the modulation of trap-assisted tunneling and nonlinear 2D band shifts in response to the gate control. Furthermore, the quaternary logic operation based on the triple NDR with the largest PVCR of 137 is achieved by the correlated biasing of the WSe2 DLHJ device.

Design of quaternary MIN and MAX circuits using graphene nanoribbon field effect transistors

This paper presents the design of digital logic schematics in quaternary logic. The quaternary logic is considered as best choice over the conventional two-valued logic due to its advantages such as faster computations, large memory storage, reduced interconnect length, ability to transmitting and receiving the large information, and simplification in testing. These advantages allow designing high performance circuit’s in the future integrated circuits. The new method is projected to develop the quaternary logic circuits utilizing graphene nanoribbon field effect transistors (GNRFETs). The quaternary logic circuits are developed based on GNRFETs wonderful properties, such as controlling the threshold voltage by changing the GNR width. This property makes them compatible to develop the multi-threshold digital circuits. To ensure the functionality of the digital circuits, the GNRFET based quaternary minimum (MIN) and maximum (MAX) circuits are developed. The proposed designs are simulated extensively in HSPICE tool for performance analysis. In comparison with the quaternary CNTFET based circuits, the proposed circuits optimized by 67.13%, 18.7%, 73.16% and 25.88%, in power consumption, delay, power delay product (PDP) and circuit area, respectively.

Design of Low Power Less Leakage Quarternary Adder Using CMOS

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

A creative concept for designing and simulating quaternary logic gates in quantum-dot cellular automata

A creative concept for designing and simulating quaternary logic gates in quantum-dot cellular automata

Design and Simulation of Innovative QCA Quaternary Logic Gates

AbstractThis paper proposes a new cell configuration for quaternary Quantum Cellular Automata (QQCA) based on the calculation of polarization. The proposed QQCA cell is based on a three‐particle system that creates instability within a cell in the gate design. Therefore, a single‐particle system or binary QCA (bQCA) technology and a two‐particle system or Ternary QCA (TQCA) technology have been used to implement quaternary logic. The proposed cell can be implemented in two layers or in one, using input and output drives. According to the dimensions of the proposed model for QQCA and simulation of basic gates, designing with this cell is quite optimal; it requires five cells in the design of the AND and OR gates and two cells in the design of the NOT gate. Based on the number of cells used in the basic gates, the total area in the AND and OR gates is 576 × 10−6 µm2 and in the NOT gate is 276 × 10−6 µm2. The base gates are fully optimized and latency is equal to 0.25 clockcycle or 0.25 × 10−12s, which is reduced in comparison with prior works. Also, the power consumption of a cell in terms of quantum calculation and the proposed model is also investigated.

An Energy-Efficient Crosstalk Reduction Strategy for On-Chip Buses Using Carbon-Based Transistors and Interconnects

This paper presents a novel crosstalk reduction scheme based on quaternary logic that eliminates the harmful transition patterns and protects communication channels of system-on-chips (SoCs) against crosstalk. The proposed architecture is designed based on gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) codec and converter modules considering multi-walled carbon nanotube (MWCNT), and multilayer graphene nanoribbon (MLGNR) interconnects at 10 nm technology. The simulation results indicate that our proposed approach reduces the delay and power-delay product (PDP) on average by 52% and 36%, respectively, for MWCNT interconnects compared to the basic architecture. These improvements are 50% and 35% for the MLGNR interconnects. Moreover, utilizing the MLGNR interconnects instead of MWCNT interconnects in the proposed coded system leads to a 61% shorter crosstalk delay and 65% lower PDP. In addition, the proposed coding scheme leads to 35% reduction in the occupied area and improves PDP, on average, by 37%, and 26% for the MWCNT and MLGNR buses, respectively, as compared to their binary counterparts.

Application of discrete mathematics, tetralogic and architecture of superscalar systems in measurement metrology of automated control systems

The article is dedicated to the consideration of the role and significance of the quaternary logic in automated control systems. The methodology of reduction and application of the principle of ergodicity in measurement metrology in automated process control systems is presented. The optimization role of the tools used in solving of hybrid technological and telemetry problems is emphasized.

Prediction of a Two-Transistor Vertical QNOT Gate

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.