An Energy-Efficient Crosstalk Reduction Strategy for On-Chip Buses Using Carbon-Based Transistors and Interconnects

Abstract

This paper presents a novel crosstalk reduction scheme based on quaternary logic that eliminates the harmful transition patterns and protects communication channels of system-on-chips (SoCs) against crosstalk. The proposed architecture is designed based on gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) codec and converter modules considering multi-walled carbon nanotube (MWCNT), and multilayer graphene nanoribbon (MLGNR) interconnects at 10 nm technology. The simulation results indicate that our proposed approach reduces the delay and power-delay product (PDP) on average by 52% and 36%, respectively, for MWCNT interconnects compared to the basic architecture. These improvements are 50% and 35% for the MLGNR interconnects. Moreover, utilizing the MLGNR interconnects instead of MWCNT interconnects in the proposed coded system leads to a 61% shorter crosstalk delay and 65% lower PDP. In addition, the proposed coding scheme leads to 35% reduction in the occupied area and improves PDP, on average, by 37%, and 26% for the MWCNT and MLGNR buses, respectively, as compared to their binary counterparts.