Quasi-static Capacitance-voltage Measurements Research Articles

Sources of error and methods to improve accuracy in interface state density analysis using quasi-static capacitance–voltage measurements in wide bandgap semiconductors

Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C−ψS technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C−ψS technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1/CS∗2 vs ψS plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1/CS∗2 vs ψS plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.

Sensitivity of D<sub>it</sub> Extraction at the SiO<sub>2</sub>/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.

Temperature dependent quasi-static capacitance-voltage characterization of SiO2/β-Ga2O3 interface on different crystal orientations

The interface trap density (Dit) of the SiO2/β-Ga2O3 interface in (2¯01), (010), and (001) orientations is obtained by the Hi-Lo method with the low frequency capacitance measured using the Quasi-Static Capacitance-Voltage (QSCV) technique. QSCV measurements are carried out at higher temperatures to increase the measured energy range of Dit in the bandgap. At room temperature, higher Dit is observed near the band edge for all three orientations. The measurement at higher temperatures led to an annealing effect that reduced the Dit value for all samples. Comparison with the conductance method and frequency dispersion of the capacitance suggests that the traps at the band edge are slow traps which respond to low frequency signals.

Switch the n-type to ambipolar transfer characteristics by illumination in n-type pentacene-based organic field-effect transistors

This work investigates the suppression of n-channel and the switch of transfer characteristics (from n-type to ambipolar) by illumination in n-type pentacene-based organic field-effect transistors (OFETs). The illumination outcomes differently on the output characteristics of OFETs, which markedly decreases the magnitude of drain current (n-channel) and shifts the turn-on voltage to a higher positive bias in the n-type regime, but induces the formation of p-channel in the p-type regime. We attribute that the trapped negative charges in the device as induced by illumination electrostatically shield the effective electrical field applied to the gate with source/drain electrodes and modulate the device performance. The result of quasi-static capacitance–voltage measurement agrees well with the modulations of the transfer characteristics for n-type OFETs by illumination. In addition, the de-trapping of charges recovers the n-type only output characteristics of pentacene-based OFETs. This study highlights the unique photo responses of n-type pentacene-based OFETs to the development of phototransistors of distinct output characteristics operated in n- and p-type regime.

Characterization of Vth‐instability in Al2O3/GaN/AlGaN/GaN MIS‐HEMTs by quasi‐static C‐V measurement

AbstractThe threshold‐voltage (Vth) instability in AlGaN/GaN MIS‐HEMTs with ALD‐Al2O3 (15 nm) as gate dielectrics is systematically investigated by dc current‐voltage (I‐V), high‐frequency capacitance‐voltage (C‐V) (HFCV), and quasi‐static C‐V (QSCV) characterizations. For Al2O3/GaN/AlGaN/GaN MIS diodes, tiny Vth hysteresis (ΔVth) appears in double‐mode (up and down sweep) HFCV measurements if the maximum forward bias (VF,max) is only set to 0 V, while an apparent clockwise ΔVth (as large as 0.9 V) emerges as VF,max is increased to +5 V. The stability of Vth in the corresponding MIS‐HEMTs is thus studied by increasing the maximum VGS (VGS,max) in the measurement of double‐mode transfer characteristics. Significant clockwise ΔVth also occurred once the VGS,max exceeds +1.1 V, and it increased to ∼1 V at VGS,max= +3 V. Such Vth‐instability is absent in AlGaN/GaN HEMTs. It is suggested that the acceptor‐like deep states at Al2O3/GaN interface account for the Vth‐instability in Al2O3/GaN/AlGaN/GaN MIS‐HEMTs, and their filling and emission processes are successfully captured by QSCV measurements. The interface state density detected is about 4.6×1012 cm‐2 using 1 Hz QSCV. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Trapping of electrons in metal oxide-polymer memory diodes in the initial stage of electroforming

Metal oxide-polymer diodes require electroforming before they act as nonvolatile resistive switching memory diodes. Here we investigate the early stages of the electroforming process in Al/Al2O3/poly(spirofluorene)/Ba/Al diodes using quasistatic capacitance-voltage measurements. In the initial stage, electrons are injected into the polymer and then deeply trapped near the poly(spirofluorene)-Al2O3 interface. For bias voltages below 6 V, the number of trapped electrons is found to be CoxideV/q with Coxide as the geometrical capacitance of the oxide layer. This implies a density of traps for the electrons at the polymer-metal oxide interface larger than 3×1017 m−2.

Passivation by N Implantation of the SiO2/SiC Acceptor Interface States: Impact on the Oxide Hole Traps and the Gate Oxide Reliability

AbstractThis study compares p-MOS capacitors fabricated on N+ implanted and on virgin 4H-SiC. The former sample have N at the SiO2/SiC interface, the latter have not. To investigate the presence of deep and shallow hole traps at the SiO2/SiC interface, high frequency and quasi-static capacitance voltage measurements under dark have been compared for bias sweeping from accumulation to depletion and from depletion to accumulation, the latter after white light illumination. The presence of N has an effect on the density of the shallow donor like traps but none effect on the deep ones. The positive charge trapped in the oxide and/or at the oxide interface after equivalent tunneling hole injection have been compared and are equivalent. Time dependent dielectric breakdown tests have been compared too. The oxide grown on N+implanted SiC broken at lower electric field.

Study of charge storage characteristics of memory devices embedded with metallic nanoparticles

The structural and electrical properties of thin silicon dioxide and hafnium oxide dielectric stacks with embedded gold nanoparticles obtained by electron-beam evaporation are reported. Transmission electron microscopy shows that the nanoparticles have a mean diameter of 2.6 nm and a sheet density of 3.3×10 12 cm −2. High-frequency and quasi-static capacitance–voltage measurements of MOS capacitors reveal that charge injection and storage takes place in the nanoparticle dielectric stack at low gate voltages. Efficient charge trapping occurs only in the case of holes injected from the substrate. Programming and retention time measurements indicate that the fabricated nanoparticle dielectrics are attractive for low-voltage non-volatile memory applications.

Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods

AbstractInterface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).

Impact of surface chemical treatment on capacitance-voltage characteristics of GaAs metal-oxide-semiconductor capacitors with Al2O3 gate dielectric

The authors examine the impact of two different chemical surface treatment methods on capacitance-voltage characteristics of GaAs metal-oxide-semiconductor (MOS) capacitors using NH4OH and (NH4)2S prior to atomic layer deposition (ALD) of Al2O3. In both cases, x-ray photoelectron spectroscopy data confirm the removal of As2O3∕As2O6 upon Al2O3 deposition. However, Ga–O bonds appear to incorporate in the final gate stack at the Al2O3∕GaAs interface. MOS capacitors exhibit a steep transition from accumulation to depletion as well as very low leakage current density indicating high quality of ALD-Al2O3. The midgap interface trap density was evaluated to be (∼3–5)×1011∕cm2eV using the Terman method. In addition, quasistatic capacitance-voltage (C-V) measurement confirms the formation of true inversion layer in GaAs using both chemical treatment protocols. However, sulfur-passivated GaAs demonstrates better frequency dispersion behavior and slightly smaller capacitance equivalent thickness than hydroxylated GaAs. A statistical study substantiates the reproducibility of these results.

Influence of polymer gate dielectrics on n-channel conduction of pentacene-based organic field-effect transistors

This work elucidates the way polymer gate dielectrics affect the accumulation and transport of charge carriers in the active layer of organic field-effect transistors (OFETs). Incorporating a poly(vinyl alcohol) polymer interfacial film and another cross-linked poly(4-vinyl phenol) layer as a double-layer gate dielectric causes the pentacene-based OFETs to exhibit effective n-channel conduction of a saturated, apparent pinch-off drain-source current with the electron mobility of ∼0.012cm2V−1s−1. The formation of an n channel in the pentacene layer is supported by the increased capacitance that is identified by the quasistatic capacitance-voltage measurements of devices with the metal-insulator-semiconductor configuration, biased at a positive gate voltage, in the n-type accumulation regime.

Characterization of the Si − SiO2 Interface Following Room Temperature Ammonia Plasma Exposure

The electrical properties of the interface following nitridation by ammonia plasma exposure at room temperature indicate that a high density of interface defects and charges is generated by the plasma exposure. Combined high-frequency and quasistatic capacitance-voltage measurements show a dramatic increase in the midgap defect density and interface charge, while quasi-steady-state photoconductivity decay measurements indicate a large increase in carrier recombination at the surfaces, as measured by an increase in the emitter saturation current density. The majority of the defects are not paramagnetic and are annealed out by a thermal treatment at 400°C. However, some defects are also generated by the ammonia plasma exposure which is not removed by subsequent thermal treatments. A combination of ammonia plasma treatment and a subsequent 400°C anneal results in good interface passivation, despite the generation of additional paramagnetic defects, making oxynitride layers produced in this way attractive for potential photovoltaic applications.

Tunable threshold voltage and flatband voltage in pentacene field effect transistors

Charged interface states are introduced by UV-ozone treatment of a polymer gate dielectric, parylene, prior to deposition of the organic semiconductor, pentacene, thereby modifying the organic field effect transistor (OFET) operation from enhancement to depletion mode. Quasistatic capacitance-voltage measurements and the corresponding current-voltage characteristics show that the threshold voltage VT and flatband voltage VFB can be shifted by over +50V, depending on the ozone exposure time. This work demonstrates that careful control of the semiconductor-insulator interface state densities is essential to VT and VFB control and the fabrication of reliable OFET integrated circuits.

Quasi-Static Capacitance–Voltage Characteristics of Polycrystalline Silicon Thin-Film Transistors

We have investigated the quasi-static capacitance–voltage (QSCV) characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs), focusing on how the integration time for the capacitance measurement affects the QSCV curves. We have found that the response time of the carriers in the OFF state of the TFTs can be estimated from the QSCV results. QSCV measurements with external illumination enable us to estimate the surface depletion capacitance of TFTs. We have also found that the QSCV characteristics vary with the channel length of TFTs, indicating that the channel length dependence must be taken into account when making a model of TFT capacitance in the OFF state.

Detection of DNA recognition events using multi-well field effect devices

We proposed the multi-well field effect device for detection of charged biomolecules and demonstrated the detection principle for DNA recognition events using quasi-static capacitance-voltage (QSCV) measurement. The multi-well field effect device is based on the electrostatic interaction between molecular charges induced by DNA recognition and surface electrons in silicon through the Si(3)N(4)/SiO(2) thin double-layer. Since DNA molecules and DNA binders such as Hoechst 33258 have intrinsic charges in aqueous solutions, respectively, the charge density changes due to DNA recognition events at the Si(3)N(4) surface were directly translated into electrical signal such as a flat band voltage change in the QSCV measurement. The average flat band shifts were 20.7 mV for hybridization and -13.5 mV for binding of Hoechst 33258. From the results of flat band voltage shifts due to hybridization and binding of Hoechst 33258, the immobilization density of oligonucleotide probes at the Si(3)N(4) surface was estimated to be 10(8) cm(-2). The platform based on the multi-well field effect device is suitable for a simple and arrayed detection system for DNA recognition events.

Electrical properties of InAlP native oxides for metal–oxide–semiconductor device applications

Data are presented on the insulating properties and capacitance–voltage characteristics of metal–oxide–semiconductor (MOS) device-thickness (below ∼100nm) native oxides formed by wet thermal oxidation of thin InAlP epilayers lattice matched to GaAs. Low leakage current densities of J=1.4×10−9A∕cm2 and J=8.7×10−11A∕cm2 are observed at an applied field of 1MV∕cm for MOS capacitors fabricated with 17 and 48nm oxides, respectively. Transmission electron microscopy images show that the In-rich interfacial particles which exist in 110nm oxides are absent in 17nm oxide films. Quasistatic capacitance–voltage measurements of MOS capacitors fabricated on both n-type and p-type GaAs show that the InAlP oxide–GaAs interface is sufficiently free of traps to support inversion, indicating an unpinned Fermi level. These data suggest that InAlP native oxides may be a viable insulator for GaAs MOS device applications.

Process damage assessment of a low energy inductively coupled plasma-based neutral source

In this article, we report process damage studies using a low energy inductively coupled plasma-based neutral stream source. Low energy neutrals are generated by the surface reflection neutralization method. Quasistatic capacitance-voltage measurement results of this work demonstrate that this low energy neutral source, which provides controllable fast neutrals for cleaning applications, induces much less damage than a pulsed inductively coupled plasma source. Most of the neutral process damage is caused by ultraviolet photons escaping from the plasma source zone. The process-induced damage by fast neutrals increases as the reflector bias is lowered. The fast neutral process damage also increases with the rf power. Unlike the neutral process-induced damage, the damage induced by pulsed plasmas is found to be a function of both the gas composition and rf pulsed frequencies.

Electrical Characterisation of polymer heterojunction light-emitting diodes

We have demonstrated that the efficiency of poly( p-phenylene vinylene) light-emitting diodes (LEDs), with aluminium contacts, can be increased by a factor 60 through use of a poly( p-pyridine-2,5-diyl) electron-transporting layer. We report an investigation of single and multilayer LEDs using quasi-static capacitance-voltage measurements.

Non-quasistatic simultaneous HF/LF-CV measurements for rapid characterization of MOS structures

We report rapid, non-quasistatic CV (capacitance–voltage) measurements for a comprehensive characterization of MOS structures. The purpose is to speed up and simplify the characterization of simple MOS test structures in a process line environment. This approach replaces the time-consuming successive application of several CV tools by one accurate and rapid technique. Contrary to quasistatic CV measurements, the use of faster gate voltage ramp rates enables a drastic reduction of the total time for the data acquisition for the characterization of high quality silicon MOS structures. The simultaneous measurement of the high frequency (HF)- and the low frequency (LF)-MOS capacitance from deep depletion toward accumulation in a non-quasistatic mode permits the determination of the density of fast interface states D it( E) from midgap to the flatband energy level, the generation lifetime τ g( x g), and the doping profile N( x d). The doping profile is corrected for voltage stretch out due to the generated inversion charge and recharges of interface traps. To speed up the relaxation process for the determination of the generation lifetime, a gate voltage ramp was used after pulsing into deep depletion, instead of a constant voltage. Driving the MOS capacitor from deep depletion toward accumulation with a linear gate voltage ramp causes a rapid relaxation of the depleted MOS capacitor to the equilibrium state. To calculate the generation active depletion width x g, the equilibrium depletion width in inversion x f must be known. x f can be conveniently determined from the sharply marked equilibrium point at the transition from generation to recombination. Consequently no extra measurement time is required for the determination of x f. The technique proposed is also applicable for the characterization of MOS capacitors with very thin oxides below 10 nm.

A novel two-step etching process for reducing plasma-induced oxide damage

During plasma etching, a large amount of charging current due to plasma can flow through the gate oxide near the endpoint, resulting in the degradation of thin gate oxide. In this paper, a two-step etching process using reactive ion etching (RIE) following wet etching is proposed to reduce the gate oxide charging current. The characteristics of the proposed process for gate oxide protection are characterized by time-dependent dielectric breakdown (TDDB), high-frequency capacitance-voltage (HFCV), and quasistatic capacitance-voltage (QSCV) measurements. From measurement results, it is shown that degradation of the gate oxide is dramatically eliminated by the proposed two-step etching method as compared with that using pure RIE. Therefore, the proposed two-step etching process can replace the pure dry etching process to reduce the plasma-induced gate oxide damage.