Quasi-static Capacitance-voltage Research Articles

Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods

AbstractInterface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).

Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors

We analyze charge accumulation and depletion behaviors from C–V curves at various gate voltages, ramp rates and sweep directions in pentacene OTFTs. The polycrystalline property of the pentacene layer has lead to carrier charge and discharge processes in the channel layer by a trap-controlled transport mechanism. We apply such processes to describe C–V profiles at various ramp rates. Hysteresis can be observed from C–V curves at faster ramp rates. The phenomenon can be attributed to the difference of the relaxation time of carrier trap and detrap processes. As the ramp rate becomes slower, hysteresis disappears since most carriers are able to interact with the gate stress. And beyond this ramp rate, the corresponding threshold voltages are then kept at constant values, despite the existence of traps. Furthermore, low-mobility carriers (mobile ions or impurities) participate in the charge accumulation and depletion when the ramp rate is even slower, which results in a skew of C–V profiles. Finally, we extend the C–V measurement to devices with different channel lengths.

Enhanced Channel Mobility Materials for MOSFETs on Si Substrates

MOS high-k/metal devices with Ge and GaAs semiconductors were used to fabricate PMOS and NMOS devices, respectively. Selective epitaxially grown (SEG) Ge PMOSFETs with a 2× enhanced IDsat and greater than 2× improvement in hole mobility compared to Si PMOSFETs. Buried-channel (BC) Ge1-xCx PMOSFETs showed a 2× enhancement in IDsat over Si control PMOSFET and ~1.5× improvement in effective mobility over universal curve for Si. The corresponding enhancement for surface channel (SC) Ge1-xCx PMOSFETs was 3× and ~2.5×, respectively. The Ion/Ioff ratio for (BC) Ge1-xCx was greater than 5×104. GaAs NMOS capacitors using two different chemical surface treatments NH4OH and (NH4)2S prior to ALD-Al2O3 deposition were examined. Both treatments remove As2O3/As2O6 upon Al2O3 deposition and unpinned the Al2O3/GaAs interface. However (NH4)2S has better frequency dispersion behavior and slightly smaller capacitance equivalent thickness (CET) than NH4OH treatment. Quasi-static CV measurement confirmed formation of a true inversion layer in GaAs.

Impact of surface chemical treatment on capacitance-voltage characteristics of GaAs metal-oxide-semiconductor capacitors with Al2O3 gate dielectric

The authors examine the impact of two different chemical surface treatment methods on capacitance-voltage characteristics of GaAs metal-oxide-semiconductor (MOS) capacitors using NH4OH and (NH4)2S prior to atomic layer deposition (ALD) of Al2O3. In both cases, x-ray photoelectron spectroscopy data confirm the removal of As2O3∕As2O6 upon Al2O3 deposition. However, Ga–O bonds appear to incorporate in the final gate stack at the Al2O3∕GaAs interface. MOS capacitors exhibit a steep transition from accumulation to depletion as well as very low leakage current density indicating high quality of ALD-Al2O3. The midgap interface trap density was evaluated to be (∼3–5)×1011∕cm2eV using the Terman method. In addition, quasistatic capacitance-voltage (C-V) measurement confirms the formation of true inversion layer in GaAs using both chemical treatment protocols. However, sulfur-passivated GaAs demonstrates better frequency dispersion behavior and slightly smaller capacitance equivalent thickness than hydroxylated GaAs. A statistical study substantiates the reproducibility of these results.

Influence of polymer gate dielectrics on n-channel conduction of pentacene-based organic field-effect transistors

This work elucidates the way polymer gate dielectrics affect the accumulation and transport of charge carriers in the active layer of organic field-effect transistors (OFETs). Incorporating a poly(vinyl alcohol) polymer interfacial film and another cross-linked poly(4-vinyl phenol) layer as a double-layer gate dielectric causes the pentacene-based OFETs to exhibit effective n-channel conduction of a saturated, apparent pinch-off drain-source current with the electron mobility of ∼0.012cm2V−1s−1. The formation of an n channel in the pentacene layer is supported by the increased capacitance that is identified by the quasistatic capacitance-voltage measurements of devices with the metal-insulator-semiconductor configuration, biased at a positive gate voltage, in the n-type accumulation regime.

Electromechanical characterization of low actuation voltage RF MEMS capacitive switches based on DC CV measurements

This paper reports on the enhancements introduced into the ITC-irst RF MEMS multi-user fabrication process, which have been assessed by means of the electromechanical characterization of a set of test structures consisting of low actuation voltage capacitive switches. A simple quasistatic CV measurement has been used to extract the switch capacitance in both the on and off states ( C on and C off) and the voltage needed for the actuation of the different designs. The devices under test use folded serpentine springs and large area actuation electrodes to decrease the pull-in voltage. The spring constant of the suspensions is used to control the actuation voltage of the different designs with a slight increase of the overall size and without affecting the switching performance at higher frequencies. The introduction of a floating metal layer into the flow of the fabrication process has allowed a great increase in the off state capacitances, getting C off/ C on ratios up to 10 times greater than the ones obtained for the same structures without this feature.

Modelling the threshold-voltage shift of polymer thin-film transistors under constant and variable gate-bias stresses

Polymer thin-film transistors based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) semiconductors are fabricated by a spin-coating process and characterized. The effects of gate-bias stress on the devices at room temperature are studied. Upon the gate-bias stress, the saturation current decreases; threshold voltage shifts toward the negative direction, but carrier mobility remains essentially constant. Quasi-static capacitance–voltage analysis on a metal-oxide-semiconductor capacitor structure is used to clarify the physical mechanism of the threshold-voltage shift. A model for the threshold-voltage shift under constant and variable gate-bias stresses is proposed and shows good agreement with experimental data.

Effect of hydrogenation on the memory properties of Si nanocrystals obtained by inductively coupled plasma chemical vapor deposition

Effect of hydrogenation on memory properties has been studied for metal-oxide-semiconductor (MOS) structures with Si nanocrystals fabricated using inductively coupled plasma chemical vapor deposition and subsequent annealing. Hydrogenation induces a drastic increase of a dip in the quasistatic capacitance-voltage (C-V) curve of the MOS capacitor, caused by the reduction of the interface states due to hydrogen passivation. This is consistent with high-frequency C-V measurements showing more well-defined curves with less distortion in hydrogenated samples. After hydrogenation, the MOS device shows a significantly larger decrease of flatband voltage shift in electron charging than in hole charging, indicating more effective passivation of the defect states related to the electron charging. A longer retention time is found for electron charging after hydrogenation, but almost no change of charge loss rate for hole charging. These results suggest that an asymmetry exists in the effect of hydrogenation between electron and hole storage.

Quasi-Static Capacitance–Voltage Characteristics of Polycrystalline Silicon Thin-Film Transistors

We have investigated the quasi-static capacitance–voltage (QSCV) characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs), focusing on how the integration time for the capacitance measurement affects the QSCV curves. We have found that the response time of the carriers in the OFF state of the TFTs can be estimated from the QSCV results. QSCV measurements with external illumination enable us to estimate the surface depletion capacitance of TFTs. We have also found that the QSCV characteristics vary with the channel length of TFTs, indicating that the channel length dependence must be taken into account when making a model of TFT capacitance in the OFF state.

Application of junction capacitance measurements to the characterization of solar cells

The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.

Hysteresis in organic field-effect devices: Simulated effects due to trap recharging

Current organic field-effect transistors feature predominantly undesirable hysteresis effects which appear also in the capacitance-voltage (CV) characteristics of organic metal-oxide-semiconductor (MOS) capacitors. So far, these effects are not sufficiently characterized experimentally and their origin is even less understood. In the literature one finds presumptions that they are caused by trap recharging or by mobile ions (in the organic semiconductor or in the insulator). In order to check the first of these presumptions, detailed numerical simulations have been carried out. Hysteresis in the field effect is studied at best in the MOS capacitor without the additional influence of the source/drain contacts of the transistor. Although there are differences between quasistatic and dynamic measurements, our simulations are done for the quasistatic CV characteristics since they already give the desired information for the understanding of the hysteresis effects. Organic semiconductors with different types of traps of different energetic positions, concentrations, and energetic and spatial distributions are considered and their parameters are varied in a wide range. Trap recharging is connected with the transport of the emitted (captured) carriers from (to) the traps during the voltage sweep. It is demonstrated that rather different types of hysteresis can occur thereby. All of the simulated shapes of the hysteresis are qualitatively different from that one which is typically observed experimentally. Therefore, it should be ruled out that the hysteresis observed in organic MOS devices is solely caused by trap recharging. The observed changes of the CV characteristics for a variation of different measuring conditions and parameters indicate that the hysteresis is caused by at least two different processes. We suppose that the origin of the hysteresis in organic devices is a combination of slow transport (polarons or mobile ions) with a reaction other than trap recharging, e.g., the direct polaron-bipolaron reaction or a complex formation reaction of polarons/bipolarons with counterions.

Detection of DNA recognition events using multi-well field effect devices

We proposed the multi-well field effect device for detection of charged biomolecules and demonstrated the detection principle for DNA recognition events using quasi-static capacitance-voltage (QSCV) measurement. The multi-well field effect device is based on the electrostatic interaction between molecular charges induced by DNA recognition and surface electrons in silicon through the Si(3)N(4)/SiO(2) thin double-layer. Since DNA molecules and DNA binders such as Hoechst 33258 have intrinsic charges in aqueous solutions, respectively, the charge density changes due to DNA recognition events at the Si(3)N(4) surface were directly translated into electrical signal such as a flat band voltage change in the QSCV measurement. The average flat band shifts were 20.7 mV for hybridization and -13.5 mV for binding of Hoechst 33258. From the results of flat band voltage shifts due to hybridization and binding of Hoechst 33258, the immobilization density of oligonucleotide probes at the Si(3)N(4) surface was estimated to be 10(8) cm(-2). The platform based on the multi-well field effect device is suitable for a simple and arrayed detection system for DNA recognition events.

Electrical properties of InAlP native oxides for metal–oxide–semiconductor device applications

Data are presented on the insulating properties and capacitance–voltage characteristics of metal–oxide–semiconductor (MOS) device-thickness (below ∼100nm) native oxides formed by wet thermal oxidation of thin InAlP epilayers lattice matched to GaAs. Low leakage current densities of J=1.4×10−9A∕cm2 and J=8.7×10−11A∕cm2 are observed at an applied field of 1MV∕cm for MOS capacitors fabricated with 17 and 48nm oxides, respectively. Transmission electron microscopy images show that the In-rich interfacial particles which exist in 110nm oxides are absent in 17nm oxide films. Quasistatic capacitance–voltage measurements of MOS capacitors fabricated on both n-type and p-type GaAs show that the InAlP oxide–GaAs interface is sufficiently free of traps to support inversion, indicating an unpinned Fermi level. These data suggest that InAlP native oxides may be a viable insulator for GaAs MOS device applications.

Improvements in the Quasi-static Capacitance–Voltage Characterization of Semiconductor–Insulator Interface States (Si/SiO2)

The quasi-static capacitance–voltage determination of the electron density of states as a function of energy at the semiconductor–insulator interface is addressed. The respective effects are analyzed of random and systematic errors in a measured capacitance–voltage characteristic on the interface-state distribution derived. The random errors show up as fluctuations that grow indefinitely in magnitude as the energy approaches either band edge. Systematic errors are manifested in under- and overshoots near the band edges. The most important are the systematic errors associated with the estimation of the insulator capacitance and the identification of the relationship between the semiconductor surface potential and the applied voltage. A method for minimizing the errors is proposed. It is noted that the method should enable one to substantially expand the accessible energy range and to significantly improve the accuracy to which the density of states is evaluated. These advantages are confirmed by an experiment on the Si/SiO2 interface. It is found that the energy range can be made as wide as about 0.9 eV and the accuracy of the semiconductor surface potential can be improved to about 0.1 meV, so that the integrated density of states can be determined to within about 5 × 107 cm–2. It is inferred from the experimental data that the interface states are concentrated near the conduction band edge and are due to positive oxide fixed ions rather than Pbcenters. The ions should act as electron traps involved in tunnel electron exchange with the conduction band of the silicon.

Charge dynamics of silicon nanocrystals in MOS capacitors

In this paper we present a study of room temperature quasi-static capacitance–voltage and current–voltage characteristics of MOS capacitors containing silicon nanocrystals (Si-nc). We use the feedback charge method to measure simultaneously and independently the displacement current and the leakage current. As a result, an excess current attributed to the charging of the Si-nc with electrons and, simultaneously, a voltage shift of the capacitance are found. These excess current and voltage shift are found to strongly depend on the voltage scan rate and the initial state of charge in the Si-nc determined by a stress procedure applied before measurements. At each stage, the charge dynamics of the Si-nc is compared with that in reference samples and discussed. It is found that an average of 50% of Si-nc are charged by electrons.

Charge dynamics of silicon nanocrystals in MOS capacitors

In this paper we present a study of room temperature quasi-static capacitance–voltage and current–voltage characteristics of MOS capacitors containing silicon nanocrystals (Si-nc). We use the feedback charge method to measure simultaneously and independently the displacement current and the leakage current. As a result, an excess current attributed to the charging of the Si-nc with electrons and, simultaneously, a voltage shift of the capacitance are found. These excess current and voltage shift are found to strongly depend on the voltage scan rate and the initial state of charge in the Si-nc determined by a stress procedure applied before measurements. At each stage, the charge dynamics of the Si-nc is compared with that in reference samples and discussed. It is found that an average of 50% of Si-nc are charged by electrons.

Analysis of carrier generation lifetime in strained-Si/SiGe heterojunction MOSFETs from capacitance transient

Carrier generation lifetime ( τ g) in strained-Si/SiGe has been investigated using capacitance transient method in MOS structure. Interface properties of thermally grown gate oxide on strained-Si/SiGe has been studied prior to transient capacitance measurements. Average midgap value of interface state density ( D it) extracted from quasi-static CV measurement is around 2×10 10 to 5×10 10 cm −2 eV −1 for both strained-Si and bulk-Si samples. The observed non-linear behavior of capacitance transient characteristics for strained-Si/SiGe heterostructure are due to the carrier confinement in the potential wells caused by virtue of the valence band and conduction band discontinuities. Generation lifetime in strained-Si and SiGe buffer layer estimated from the segments of Zerbst plot having different slopes. The value of generation lifetime in strained-Si, SiGe buffer and co-processed bulk-Si is ranges from 120 to 170 μs, 20 to 90 μs and 177 μs, respectively.

Analyzes of field effect devices based on poly(3-octylthiophene)

Poly(3-octylthiophene) (P3OT) based MOS capacitors and transistors have been prepared. The spin-coated P3OT-layers have been investigated by ellipsometry. The measured index of refraction and the gap energy are n=1.8 and E G=2 eV, respectively. The layer thickness has been varied by the technological parameters of the deposition process from 65 nm down to about 10 nm. Quasi-static and dynamic capacitance voltage measurements on the capacitors prove an unintentional p-doping and indicate that layers up to about 30 nm are fully depleted. An unintentional doping concentration of approximately 5×10 17,…,2×10 18 cm −3 has been estimated by analytical approximations and comparison with numerical two-dimensional (2D) simulations. Both types of devices show hysteresis effects which have been already observed and analyzed for devices based on arylamino-poly-( p-phenylene-vinylene) and also reported for poly(3-hexylthiophene). The hysteresis is formally described by different flat band voltages for the sweep from positive to negative bias and the reverse direction. The dependence of the hysteresis on measuring and geometrical parameters allows for a qualitative discussion of the possible origin of the hysteresis. The analysis of the impedance measurements on the capacitors by estimations from the dielectric relaxation and comparison with 2D simulations is complemented by proposing an appropriate equivalent circuit. The extracted mobility perpendicular to the layer is as low as ≈5×10 −8 cm 2/V s. The thin film transistors have a subthreshold slope of S≈200 mV/dec which is rather good for an organic device. This value is in accordance with simulations and analytical calculations provided there are effectively no rechargeable trap states neither at the interface nor in the bulk. The mobilities estimated for the parallel transport are with ≈2×10 −5 cm 2/V s almost three orders of magnitude larger than for the perpendicular transport. The influence of ageing and subsequent annealing has been investigated. The results support the assumption that the high unintentional doping is at least to some extent caused by oxidation.

Evidence of charging effect in silicon nano-crystals using a feedback chargemethod with metal oxide–semiconductor capacitors

In some new types of non-volatile memory, where silicon nano-crystals(nc-Si) are implemented as a floating gate at a tunnel distance from thechannel, the evidence of charging effect in these nc-Si is observed andstudied experimentally. We present quasi-static capacitance–voltage (C–V) and current–voltage(I–V)measurements of MOS capacitors containing nc-Si based on a feedback chargemethod. Doing so we can measure simultaneously and separate the capacitancefrom leakage and excess currents. Depending on the presence or not of nc-Si in acapacitor, we observe the presence of a maximum of four peaks in the current, ofwhich only one depends on the voltage scan rate. This behaviour is explained interms of nc-Si dynamic charge and discharge and offset charge influence as well.

Evidence of room temperature charging effects of silicon nanocrystals inside metal-oxide-semiconductor capacitors using feedback charge measurements

In this paper we present a study of room temperature quasi-static capacitance–voltage C– V and current–voltage Q/ t– V characteristics of metal-oxide-semiconductor (MOS) capacitors containing silicon nanocrystals (nc-Si). We use the feedback charge method to simultaneously measure C– V and Q/ t– V. While no specific feature is observed on C– V curves, on Q/ t– V curves we can clearly identify an excess current that can be assigned to the charging effects related to the existence of the nc-Si. The position of this peak current and the evaluated density of charge stored in the nc-Si are monitored by the swiftness of measurement. A phenomenological analysis is given and a possible implication of crosstalk between the nc-Si is proposed.