QFN Package Research Articles

Warpage of QFN Package in Post Mold Cure Process of integrated circuit packaging

This research studied about warpage of QFN package in post mold cure process of integrated circuit (IC) packages using pre-plated (PPF) leadframe. For IC package, epoxy molding compound (EMC) are molded by cross linking of compound stiffness but incomplete crosslinked network and leading the fully cured thermoset by post mold cure (PMC) process. The cure temperature of PMC can change microstructure of EMC in term of stress inside the package and effect to warpage of the package due to coefficient of thermal expansion (CTE) between EMC and leadframe. In experiment, cure temperatures were varied to check the effect of internal stress due to different cure temperature after completed post mold cure for TDFN 2×3 8L. The cure temperature were varied with 180 °C, 170 °C, 160 °C, and 150°C with cure time 4 and 6 hours, respectively. For analysis, the TDFN 2×3 8L packages were analyzed the warpage by thickness gauge and scanning acoustic microscope (SAM) after take the test samples out from the oven cure. The results confirmed that effect of different CTE between EMC and leadframe due to different cure temperature resulting to warpage of the TDFN 2×3 8L packages.

A Quad-Band CMOS Linear Power Amplifier for EDGE Applications Using an Anti-Phase Method to Enhance its Linearity

This work describes the use of an anti-phase method to enhance the linearity of a quad-band CMOS linear power amplifier for EDGE applications. The anti-phase method is applied in a CMOS process, by studying the $\text {g}_{\mathrm {{m3}}}$ characteristic of the transistor and then operating the drive stage in the subthreshold region to cancel the nonlinearity of the power stage. The power amplifier is fabricated with a $0.11~\mu \text {m}$ RF CMOS process and packed with a 44-pin QFN package. It operates in the GSM-800, EGSM-850, DCS-1800, and PCS-1900 bands. Application of an EDGE signal of 2.96 dB PAPR gives measured results of 26.2 and 26.7 dBm of average output power and 19.4% and 25.6% of PAE at 915 and 1910 MHz, respectively. No digital pre-distortion and off-chip components are present.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks.

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm2 (1.2 mm2 including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

Мощные GaN-усилители в корпусах QFN: ра бота в непрерывном режиме

Мощные GaN-усилители в корпусах QFN: ра бота в непрерывном режиме

热像仪对QFN封装表面发射率环境透射率的标定

Using infrared thermal imager calibrated the epoxy molding compound(EMC), copper, copper joints surface emissivity of not separated QFN package within 40-200℃, using the above three surface calibrated the air transmittance. The results show that the direct calculation method and direct adjustment method can be well applied in the calibration of EMC, direct calculation method can be well applied in the calibration of copper joints and copper solder. The emissivity calibration results of EMC is in 0.97 or so; the emissivity calibration results of copper joints with a linear change from 0.17 to 0.35 when the temperature increased; the emissivity calibration value of copper surface increased after the first stabled. The air transmittance calibration value of EMC surface and copper joints were around 100%, fluctuated less than 2%. The experimental results could provide some corresponding parameters for infrared termograph during the process measuring QFN using temperature and cutting separation temperature.

Design of a broadband current mode class-D power amplifier with harmonic suppression

Current mode class-D power amplifiers (CMCD-PA) are attractive for fully integrated PA implementation as the output capacitance of the active device can be absorbed in the output matching network that can be realized with minimum number of components. This paper presents a simplified design approach for CMCD PA design using an integrated balun transformers. Expressions are derived for the optimum device sizing for second harmonic suppression resulting in improved efficiency. An expression of amplifier efficiency as a function of device size is is presented proving that current mode class-D amplifier yields higher higher efficiency than a class-E amplifier for the same device size. The amplifier is implemented in 130 nm CMOS process and encapsulated in QFN package. Measurement results show that the amplifier exhibits broadband response between 1.4 and 2.1 GHz with peak output power of 26.8 dBm at 1.8 GHz using a 2.4 V supply. PAE remains above 40 % for the entire range while peak PAE is 48 %. Results show a good match between simulation and measurement work. Voltage sweep of the amplifier shows that it can be used in supply modulation based LINC techniques.

A low-latency, low-overhead encoder for data transmission in the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of an encoder integrated circuit for the ATLAS Liquid Argon Calorimeter trigger upgrade. The encoder implements a low-latency and low-overhead line code called LOCic. The encoder operates at 320MHz with a latency of no greater than 21ns. The overhead of the encoder is 14.3%. The encoder is an important block of the transmitter ASIC LOCx2, which is prototyped with a commercial 0.25μm Silicon-on-Sapphire CMOS technology and packaged in a 100-pin QFN package.

Small-Cell 기지국 시스템을 위한 2.6 GHz GaN-HEMT Doherty 전력증폭기 집적회로 설계

This paper presents a 2.6 GHz Doherty power amplifier IC to enhance the back-off efficiency. In order to apply to small-cell base stations, the Doherty power amplifier was fabricated using GaN-HEMT process for high power density. In addition, the implemented Doherty power amplifier was mounted on a QFN package. The implemented GaN-HEMT Doherty power amplifier was measured using LTE downlink signal with 10 MHz bandwidth and 6.5 dB PAPR for verification. A power gain of 15.8 dB, a drain efficiency of 43.0 %, and an ACLR of -30.0 dBc were obtained at an average output power level of 33.9 dBm.

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-μm Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.

Stacking of 3D Capacitor Chips in a Package for a Compact and Reliable Component Working at High Temperature

Capacitors are everywhere in electronics. They can be used for delaying, filtering, decoupling, converting, storing, etc. Various materials and technologies are used to manufacture components with different characteristics in terms of capacitance, leakage current or breakdown voltage depending on the requirements imposed by the application field. Silicon capacitors jointly developed by Ipdia and CEA-Leti combine high performances and a level of reliability that makes them suitable for high-end applications. They are also particularly appropriate for use under harsh environmental constraints such as those encountered in oil and gas prospection [1] thanks to their very good stability versus temperature [2]. In this paper, we present the developments carried out for stacking 10 chips in a package so as to obtain a 10μF capacitor capable of working continuously at 220°C during 1000h in a down-hole environment. For a first demonstrator, 100μm-thick capacitor dies were alternatively stacked and wire-bonded onto a ceramic substrate using 60μm-thick pieces of silicon as spacers [3]. Thermal tests (thermogravimetry, aging followed by shear tests) were performed in order to qualify the epoxy glue to be spread at the interfaces. A reverse ball bonding process using a fine pitch, straight bottleneck capillary was developed to obtain very low profile loops in order to prevent the wires from touching the dies above and beneath, which would have been critical for leakage. Optical profilometry and in-line electrical tests (C and I_leak measurements) were performed at each level to monitor the device functionality during the assembly. Finally Kovar lids were used to hermetically seal the packages by reflowing a AuSn preform under a N2 atmosphere. Hermeticity was measured by Residual Gas Analysis and a pressure vs. time projection was done, showing no significant pressure increase in the cavity during the lifetime of the device. Motivated by the good electrical results (capacitance within the specification, leakage current lower than 100nA) and to go further in the miniaturization and the robustness of the device, a second demonstrator was performed using a QFN package [4]. The same assembly strategy with “off-the-shelf” dies was applied on a lead frame including innovative patterns and designed with very aggressive dimensions so as to minimize the volume of the module. A new molding compound, evaluated in terms of weight loss and processability, was used to encapsulate the stacked and wire-bonded dies. After sawing, a module with a volume less than 44mm3 was obtained and showed equally good results as the first demonstrator in terms of capacitance and leakage current. A high capacitance, high reliability module was thus realized using capacitor dies and assembly materials compatible with high temperatures up to 220°C. This opens interesting prospects for the oil and gas industry since it allows drilling deeper and reaching currently inaccessible resources. The low volume of the capacitor also makes it suitable for other application fields with more drastic size constraints such as avionics or automotive.

Investigation on Thermocompression Bonding Using Lead Free Sinterable Paste and High Lead Solder Paste for Power QFN Application

Persistently growing Power QFN packages are used in various fields especially micro-electronics, aerospace, oil and gas as well. However, the particular industries is pushing forward to reduce the use of hazardous materials in the process of manufacturing and assemblies. Thermo-compression die-attach layer is perceived to be the most critical element in power QFN packages as the increase in operating temperature requires new materials with suitable thermo-chemical properties also with suitable melting points of next generation lead free die attachment material. In this situation, Hi-lead solder (RM218: Pb92.5Sn5Ag2.5) which known as high temperature material is widely being used in most semiconductor assembly for die attach, yet it deduce few reliability challenges like solder voids, the clip tilt performance and also solder splash which has been considered as major quality issue in assembly of Power QFN packages (FET die, IC die and clip attach). As a solution, sintering epoxy paste (SPC073-3: Sn96.5/Ag3/Cu0.5) is being considered as a replacement. In this case, sintering epoxy paste demonstrating excellent electrical and thermal performance for Power QFN packages which is known to be demanded in market. Thus, this study investigates the differential pastes sintering paste and also solder paste, in order to identify best die attachment material to be used in thermo-compression bonding method. Therefore, the shear strength was resulting good indication where the sintering paste was recorded 2.4 Kg/mm meanwhile the solder paste was recorded 0Kg/mm at peak temperature of 260°C. Besides of that, the pot life seems promising as the sintering paste seems to have constant viscosity of 100Pa*s throughout the 48 hours tested while, high lead solder paste records viscosity from 100Pa*s marginally increase as the time increase which effects the inconsistency of pot life. Last but not least, the voids mechanisms proves sintering epoxy paste has the same pinhole voids as its individual, but the solder paste’s pinhole voids are not same as individuals which easily can fail when the particular shear force was applied. Hence, sintering epoxy paste could resolve the quality issue by using thermo-compression bonding method and produce the better reliability than the solder paste.

Liquid Crystal Polymer for QFN packaging: Predicted thermo-mechanical fatigue and Design for Reliability

Thermoplastic resins, such as Liquid Crystal Polymers (LCPs), have many attractive properties for microelectronic cavity package manufacturing (in particular low gas permeation and low dielectric constant). In order to reduce anisotropic mechanical properties inducing a potential fragility of the material and then a lack of reliability of the package, various approaches are currently studied in particular the addition of mineral fillers. A dedicated Design of Experiments (DoE) is performed to assess the optimal thermo-mechanical properties of the LCP compound and then the optimal composition of the package leading to the maximum operating lifetime. In this way the long-term reliability of an electronic package (Quad Flat No-lead – QFN – package) based on various formulations of the LCP composite is assessed by thermo-mechanical simulation using Finite Element Method (FEM). A Design for Reliability (DfR) methodology is proposed according to the simulation results based on Taguchi methodology. This methodology allows the determination of the optimal composition (nature/proportion/size/chemical functionalization of fillers) of the LCP package by reducing the number of experimental studies that are very time consuming.

COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.

Design of Experiment Methodology for Thermal Fatigue Reliability of Multi-row QFN Packages Based on Numerical Simulations

Design of Experiment Methodology for Thermal Fatigue Reliability of Multi-row QFN Packages Based on Numerical Simulations

A SAW-Less First Folded-Conversion Second Down-Conversion Receiver for Multistandard Broadcasting Radio Applications

A surface-acoustic-wave-less first folded-conversion and second down-conversion receiver for the AM/FM/digital radio mondiale (DRM)/digital audio broadcasting (DAB) radio standards is presented. This architecture is more suitable for broadcasting radio with ultra-narrow signal bandwidth since it relaxes the requirement on the local area (LO) generator by decreasing its tuning range. To reduce the blockers and out-of-band (OB) interferers, current amplifying and polyphase filters are introduced simultaneously. An inverter-based switched capacitor array technique is proposed in voltage-controlled oscillator (VCO) design to isolate the noise from the substrate. With a single VCO, the receiver can cover the frequency range from 100 kHz to 1.5 GHz. Without the RF pre-filters, the in-band ${\rm IIP}_{3}$ is 1.5 dBm, and the OB ${\rm IIP}_{3}$ is up to 17.4 dBm. The LO phase noise in the worst case is $-$ 119 dBc/Hz@1 MHz. The chip is fabricated in a 0.18- $\mu{\hbox{m}}$ CMOS technology, and mounted on a QFN package. It consumes only 86.4 mW under 1.8-V supply. To our best knowledge, this is first receiver reported thus far that supports all four AM/FM/DRM/DAB standards.

Structural health monitoring of solder joints in QFN package

QFN is very attractive package especially when it is used for power components. Its electrical and thermal performance turned this package to a very desirable for high speed and high power components. However the drawback of QFN package is its low reliability in applications that experience thermal cycles such as automotive and aerospace. A novel technique presented in this paper suggests a quantitative measurement tool for crack propagation in QFN solder-joints that could predict end-of-life of monitored joints. The technique that has been developed is based on serial ohmic resistance changes in solder joints as a function of crack propagation. A combination of mathematical model and measured data of solder-joints’ ohmic resistance provides a structural health monitoring tool of QFN solder-joints. This could be used as a prognostic tool to remaining useful life of QFN package.

A Triple-Band Transceiver Module for 2.3/2.5/3.5 GHz Mobile WiMAX Applications

A triple-band transceiver module for 2.3/2.5/3.5 GHz mobile WiMAX, IEEE 802.16e, applications is introduced. The suggested transceiver module consists of RFIC, reconfigurable/multi- resonance MIMO antenna, embedded PCB, mobile WiMAX base band, memory and channel selection front-end module. The RFIC is fabricated in 0.13μm RF CMOS process and has 3.5 dB noise figure(NF) of receiver and 1 dBm maximum power of transmitter with 68-pin QFN package, 8  8 mm 2 area. The area reduction of transceiver module is achieved by using embedded PCB which decreases area by 9% of the area of transceiver module with normal PCB. The developed triple-band mobile WiMAX transceiver module is tested by performing radio conformance test(RCT) and measuring carrier to interference plus noise ratio (CINR) and received signal strength indication (RSSI) in each 2.3/2.5/3.5 GHz frequency. Index Terms—Transceiver module, triple-Band, mobile WiMAX, IEEE 802.16e, RFIC, embedded PCB

Effect of Gamma-Irradiation towards Stress-Strain Curve of Single Die QFN Package

The aim of the research was to establish the relationship between stress-strain behaviour of single die Quad Flat No lead (SDQFN) and degradation by gamma irradiation. The SDQFN was exposed to Cobalt-60 with different doses from 0.5 Gy, 1.5 Gy, 5.0 Gy, 10.0 Gy and 50.0 kGy. The three-point bending technique was used to measure the flexural stress and strain of the package behaviour relations. After exposing with gamma radiation, the result showed the decreasing in the strength of the package behaviour of irradiated SDQFN when increasing the dose of gamma irradiation. The highest gamma irradiation dose used in this work produced the highest change in stress-strain behaviour of irradiated SDQFN.

Effects of Different Die and Epoxy Thickness to the QFN Package

Quad Flat No-Lead or QFN is able to provide lighter, thinner and higher performance packaging requirement with its exposed pad and leads at the package bottom for better heat dissipation. However, QFN packages possess certain weaknesses. QFN package failures are related to crack and delaminating, such as die cracking, moulding compound and solder mask interfacial delaminating. From previous projects, the epoxy thickness and die thickness plays an important role in reducing failures in QFN package. The objective of this project is to observe the effects of die and epoxy thickness. The effects on QFN are measured in the die and lead frame part. Stress towards the die is also measured: including thermal, first principle and Von Misses stress. The structural optimization is based on the Finite Element Analysis (FEA). By using ANSYS 10.0, six models were constructed, where three models were built to analyse in thickness of epoxy, and another three to study the effects on die thickness. The effect was measured by the value stress (first principle stress and Von Misses stress) and thermal strain effect, which will lead to a result of how the dimensions of the packaging will give a better tolerance towards stress.

RF System in Packages (SiP) using Integrated Passive Devices

Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. As high integration and high performance have become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which helps to achieve these goals, especially for RF packages. In the IPD process, low-loss substrate material is used, and therefore high-Q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high integration. Several cases of study will be presented and here are some highlights of them. In case one, a most straightforward SiP approach is presented using QFN package, where several dies (including IPD dies) are implemented side-by-side. This approach may give fast developing cycle times. But importantly, wire-bonding models have big impact on performance from RF packaging, and should be obtained accurately for designs. Another case of study is a stack-die package, where inter-die coupling/cross talk could be a big issue as far as electrical performance is concerned. Placement of some critical parts, such as coils in IPD and in VCO, should be investigated very carefully in design phases. This leads to a concept of ‘IC/IPD/package’ co-design. Finally, a hybrid SiP package solution, where an IPD die is embedded in a mold compound along side with a RF power amplifier die, is presented. This approach (so called ‘eWLB’ packaging), results in the shortest interconnection between dies to dies and dies to balls. With the benefit from both the IPD process and the eWLB process (where low-loss mold materials are used), this approach may lead to high electrical performance and small form-factor at the same time.