Punch-through Effect Research Articles

Physics-based 3D simulation of single event transient current in GaN high-electron-mobility transistor and super-heterojunction field-effect transistor

Physics-based 3D simulations were conducted on a GaN high-electron-mobility transistor (HEMT) and a super-heterojunction field-effect transistor (SHJFET) to investigate the single event effect mechanism under heavy ion irradiation. Most of the single event transient current in HEMT was attributed to the punch-through effect in the bulk caused by the local increase in electrostatic potential. With improved E-field management and a more favorable potential profile to suppress source electron injection, the SHJFET had a 70% lower transient current peak value compared to the HEMT.

Penetration Behavior of Jack-up Leg with Spudcan for Offshore Wind Turbine to Multi-layered Soils Using Centrifuge Tests

This study examined the jack-up spudcan penetration for a new type of offshore wind substructure newly proposed using the jack-up concept to reduce construction costs. The jack-up spudcan for offshore wind turbines should be designed to penetrate a stable soil layer capable of supporting operational loads. This study evaluated multi-layered soil conditions using centrifuge tests: loose sand over clay and loose sand–clay–dense sand. The penetration resistance profiles of spudcan recorded at the centrifuge tests were compared with the ISO and InSafeJIP methods. In the tests, a spudcan punch-through effect slightly emerged under the sand-over-clay condition, and a spudcan squeezing effect occurred in the clay-over-sand layer. On the other hand, these two effects were not critically predicted using the ISO method, and the InSafeJIP result predicted only punch-through failure. Nevertheless, ISO and InSafeJIP methods were well-matched under the conditions of the clay layer beneath the sand and the penetration resistance profiles at the clay layer of centrifuge tests. Therefore, the ISO and InSafeJIP methods well predict the punch-through effect at the clay layer but have limitations for penetration resistance predictions at shallow depths and strong stratum soil below a weak layer.

High-Performance Solar-Blind p-NiO/n-ZnO/p-Si Ultraviolet Heterojunction Bipolar Phototransistors With High Optical Gain

Ultraviolet (UV) photodetectors (PDs) have attracted significant attention for civil and military applications. Zinc-oxide (ZnO) and nickel-oxide (NiO) have been widely applied in UV-PDs owing to their wide bandgap (3.2–3.8 eV), transparency, excellent optical and electrical properties, and good chemical stability. However, UV signals are generally weak; hence, UV-PDs with high optical gain are essential. In this work, high-performance solar-blind p-NiO/n-ZnO/p-Si heterojunction bipolar phototransistors (HBPTs) were fabricated. The fabricated HBPTs exhibited a high responsivity of 9.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> A/W at a wavelength of 280 nm with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_CE</i> = –7 V, a high optical gain of 3.96 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> , and a large detectivity of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> Jones. In addition, the UV/visible rejection ratio was as high as 880. These behaviors indicate that the prepared HBPTs are good solar-blind photodetectors and suitable for the detection of weak UV signals. However, for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_CE</i> value below –7 V, (| <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_CE</i> | > 7V), the optical gain decreased owing to the punch-through effect. Furthermore, band-diagrams showed that the photogenerated electrons were blocked by the potential barrier at the NiO/ZnO interface (base–emitter junction) owing to a large conduction-band discontinuity (Δ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E_C</i> ) of 2.7 eV, which resulted in a large optical gain in the prepared HBPTs.

Low Trapping Effects and High Electron Confinement in Short AlN/GaN-On-SiC HEMTs by Means of a Thin AlGaN Back Barrier

In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a non-intentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications.

Performance limits of high voltage press-pack SiC IGBT and SiC MOSFET devices

Considering the switching frequency limit and electromagnetic interference, the selection of high voltage SiC IGBT and SiC MOSFET is confusing due to punch-through effect and bipolar characteristics of SiC IGBT. The thermal resistance, static characteristics and dynamic characteristics of SiC IGBT and SiC MOSFET module with Press-Pack packaging are measured to evaluate the switching frequency limit and electromagnetic interfere of them. The tradeoffs of SiC IGBT between switching frequency limit and electromagnetic interfere are less attractive due to the intrinsic characteristics, such as high power loss and punch-through effect. The possible solutions for SiC IGBT are proposed based on the improvement of driving resistor and driving voltage.

Breakdown Mechanism of AlGaN/GaN HEMT on 200-mm Silicon Substrate With Silicon Implant-Assisted Contacts

We present an access technology suitable for scaled gallium nitride (GaN) high electron mobility transistor (HEMT) in Ka-band. The comparison between OFF-state characteristics of a silicon implant-assisted contact and a conventional recessed Ti/Al-based Ohmic contact is presented. The transistor with source/drain extension by Si implantation has a low contact resistance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4 ~\Omega \cdot {\mathrm {mm}}$ </tex-math></inline-formula> and a sheet resistance of the implanted layer of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$67~ \Omega $ </tex-math></inline-formula> /sq. In addition to promising contact performance, transistors with source and drain extension sustain high breakdown voltage (BV) with short dimensions for high-frequency applications. The systematic study of gate–source, gate–drain, and gate length variations shows a new breakdown mechanism for implanted access technology with current flowing beneath the channel leading to an unusual correlation between source–drain spacing and BV. With a conventional titanium-alloyed contact, a punchthrough effect is responsible for the BV. Cross-sectional transmission electron microscopy and secondary ion mass spectroscopy (SIMS) characterizations on both wafers highlight a degradation of the AlGaN-based back-barrier and a high silicon concentration deep into the epitaxial stack on the implanted wafers indicating a way to improve BV with an adapted process flow.

GaN based trigate HEMT with AlGaN back-barrier layer: proposal and investigation

In the present work, we have proposed a GaN based trigate high electron mobility transistor with AlGaN back-barrier (BB) layer that effectively suppress the punch-through effects as compared to the conventional device without BB layer. Furthermore, the device performance of the proposed structure has been studied by varying the distance (t ch) between AlGaN (barrier)/GaN (channel) to AlGaN (BB)/GaN (channel) interface from 100 nm to 500 nm. It is observed that the optimization of barrier/channel to BB/channel distance (t ch) is beneficial for minimizing the off-state leakage current and thereby, a high ON/OFF ratio (∼108) and nearly ideal subthreshold slope (∼64–66 mV decade−1) is achieved. Subsequently, it is shown that the optimized distance of t ch = 300 nm results in superior breakdown voltage (∼198 V) and cut-off frequency (∼81 GHz), leading to excellent Johnson figure-of-merit. The proposed device promises great potential for use in next generations high-power microwave applications.

Hot-Electron-Induced Punch-Through (HEIP) Effect in p-MOSFET Enhanced by Mechanical Stress

Hot-carrier-induced degradation of short p-channel field-effect transistors in the presence of externally applied vertical mechanical force is investigated. The mechanical stress was induced in the devices by applying a normal load with a nanoindenter. Using finite element modeling, the induced stress to the channel was estimated to reach GPa range. It is shown that compressive mechanical stress considerably enhances the impact ionization rate and the generation of secondary electron-hole pairs. These can be trapped in the gate oxide and cause a hot-electron-induced punch-through effect and effective p-channel length reduction even after both mechanical and electrical stresses are removed. The presented findings indicate the importance of mechanical stress control and engineering for improving the device reliability.

Base-width modulation effects on the optoelectronic characteristics of n-ITO/p-NiO/n-ZnO heterojunction bipolar phototransistors

ITO/NiO/ZnO npn heterojunction bipolar phototransistors (HBPTs) with various base widths are fabricated using a radio-frequency sputtering system. The effects of base-width modulation on the optoelectronic characteristics of the prepared HBPTs are studied. The dark current of HBPTs decreases with increasing base width because the injected electrons from the emitter are recombined in the wide base region. The photocurrent increases with decreasing base width, which is attributed to higher emitter-base injection efficiency. The responsivity increases with the collector-emitter voltage (V CE) in the HBPTs with a 100 nm base width, whereas the responsivity sharply decreases at V CE > 4 V for the HBPTs with a thinner base width (80 nm) due to the punch-through effect. In contrast, the responsivity approaches saturation at large V CE for HBPTs with a thicker base width (120 nm). The responsivity and detectivity decrease with increasing incident light intensity, which is caused by an increase in the base recombination loss. The HBPTs with a base width of 100 nm exhibits the largest responsivity and detectivity; their detectivity is higher than that of HBPTs with base widths of 80 and 120 nm by approximately two and three orders, respectively.

A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices

Through the age of nanoelectronics, device dimensions are curbed, and the size of transistors is rapidly reduced. Scaling down transistors results in high-speed switching, higher density, reduced power consumption, lower transistor costs. Some of the critical issues facing scaling down transistor sizes such as punch-through effect, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage roll-off, leakage current effects various proposed structure. The evolution of the semiconductor industry from the appropriate methods CMOS into a proposed structure called TFET. The TFET is a suitable method as a critical part of the power usage in circuit boards that achieves its target to meet reverse sub-threshold slope (SS) below the temperature limit (60 mV/dec in room temperature) with often a lower drive current implicitly than a MOSFET. In this study, an effort has been made to bring the roadmap of various TFET structures like Single gated TFET, Double gated TFET, Tri gated TFET, and, finally, Heterojunction TFET.

Design of a Robust ESD Protection Device using 6H-SiC Nano-Scale GGNMOS

With the continuous shrinking of the technological nodes and the introduction of new device concepts and materials, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures which is one of the major concerns in designing robust ICs. Therefore, to improve the reliability of the ICs against ESD induced failures, extensive research efforts are being conducted. In this paper, we have presented a 6H-SiC based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device and compared the results with the 3C-SiC-based ggNMOS. To design a robust ESD protection device, some critical device parameters, such as substrate doping concentration, source/drain doping concentration, drain to substrate contact spacing, and substrate contact resistance should be optimized. The ESD protection characteristics can be improved by utilizing the near punch-through effect. It was found that the trigger voltage and hold voltage are higher in 6H-SiC than the 3C-SiC having identical device parameters. 6H-SiC shows better voltage clamping performance as the turn-on resistance of 6H-SiC is smaller compared to the 3C-SiC material. Therefore, the results show that 6H-SiC has a better performance compared to 3C-SiC and due to its higher bandgap, and can be used as a good ESD protection device. All the simulations are carried out using the Silvaco ATLAS device simulator.

Digital switch boards for IV and CV measurements of large-array Low Gain Avalanche Detectors

The High-Granularity Timing Detector (HGTD), with a time resolution of approximately 30 ps, is proposed for the ATLAS Phase II upgrade to address the challenge of greatly increased pile-up interactions. The HGTD is based on the technology of Low Gain Avalanche Detectors (LGADs). The current–voltage (IV) and capacitance–voltage (CV) measurements are important methods to study the main characteristics that can be exploited for quality controlling LGADs during production. A single probe can be controlled via computer to switch channels when using an automatic probe station, but this leaves the remaining, adjacent channels floating and results in inaccurate measurements due to the punch-through effect. We designed the digital switch boards for the IV and CV measurements of 5 × 5 and 15 × 15 LGADs arrays. With the digital switch board and probe cards, channels on a large-array LGADs can be scanned automatically during the measurement, which greatly improves the measurement efficiency. The results show that the leakage currents and noise of all channels induced by the two digital switch boards are lower than 10 pA. We show the IV and CV curves of all channels on two LGADs from Hamamatsu Photonics K. K. (HPK) with our digital switch boards. Compared with the results measured by HPK with an automatic probe station, the IV and CV curves that we measured have better uniformity and accuracy, demonstrating that the quality control of the large-array LGADs can be conducted well with our digital switch board.

All transparent high-performance solar-blind n-ITO/p-NiO/n-ZnO ultraviolet heterojunction bipolar phototransistor

All transparent high-performance solar-blind n-ITO/p-NiO/n-ZnO ultraviolet heterojunction bipolar phototransistors (HBPTs) were fabricated using a low-cost radio frequency magnetron sputtering system. In the HBPT structure, ITO, NiO, and ZnO were employed as the emitter, base, and collector, respectively. The applied voltage is across the emitter and collector, and the base is floating. The photocurrent increases with the collector–emitter voltage (VCE). The prepared HBPTs presented the highest optical gain of 7.4 × 104 and a responsivity of 1.67 × 104 A/W, at VCE = 4 V for the 280-nm illumination wavelength. As VCE exceeds 4 V, the optical gain and responsivity decrease owing to the punch-through effect. The prepared HBPTs have an ultraviolet (UV)/visible rejection ratio of more than three orders, allowing their use in practical applications as UV detectors for weak UV signals.

Beam test of a PIN-diode read out PWO calorimeter with electron energies from 5 to 40 GeV at CERN SPS

The Chinese large-area violet-light-sensitive silicon photodiode PIN is one of the candidates of the lead tungstate crystal detector readout component of the photon spectrometer in the large heavy ion collision experiment. The PIN diode was assembled with the lead tungstate crystal and the low-noise preamplifier into a complete detector unit. The beam test was carried out on the SPS accelerator at CERN. The energy resolution was measured with the electron beam energy ranging from 5 to 40 GeV. The summation correction method was discussed, and an excellent linearity of the nominal beam energy versus the peak position of the detector was obtained, which showed the punch-through effect can be ignored.

Effect of cell size reduction on the threshold voltage of UMOSFETs

UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage increase appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the increase in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the increase in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the increase in Vth. We established an analytical model for the increase in Vth. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a increase in Vth, but also it is difficult to control Vth using the conventional channel implantation method.

Lateral distribution of EAS muons measured for the primary cosmic ray energy around 100 TeV * * Supported by National Key R&D Program of China (2018YFA0404202) and National Natural Science Foundation of China (11635011, 11761141001, 11765019, 11775233)

The muonic component of the extensive air showers (EAS) is of great importance for the astroparticle physics. It carries the information about the properties of primary cosmic ray (CR) particles, such as their mass, and electromagnetic and hadronic nature. It provides a sensitive test for the hadronic interaction models, which are inevitable for describing the cascade shower development of cosmic rays in EAS experiments. The YangBaJing Hybrid Array (YBJ-HA) experiment has been in operation since the end of 2016. Surface detectors are used for the measurements of primary energy, angular direction and core position of a shower event, while underground muon detectors are used for measuring the density of muons at various locations. Using the data obtained by the YBJ-HA experiment, this work reports the first measurement of the lateral muon distribution for the primary cosmic ray energy in the 100 TeV region. The punch-through effect is evaluated via MC simulation.

Physics based non-linear large-signal analysis of multiple-graphene layer exotic pin (p++–n−–n–n++) devices and ultra-fast SPST/SPDT/SPMT switches on Si/3C-SiC (100) substrates for application in THz-communication

Multiple-Graphene-Layer (MGL) on Si/3C-SiC (100) substrate is proposed for designing of a vertically doped p++–n−–n–n++ device/switch array for Terahertz communication systems. In addition to the superior mechanical properties in Graphene, conducive–electrical and electronic properties, especially, high carrier mobility in MGL has made this a promising material for different novel applications in THz domain. A quantum-modified classical drift–diffusion (QMCLDD) mathematical model, incorporating quantum size effects, arising due to Multiple-Graphene-Layer, is developed by the authors for analysing the THz-characteristics of exotic-pin p++–n−–n–n++ devices and switches. The validity of the model is further established by comparing the simulation results with those of the experimental observations under similar electrical/thermal/structural operating conditions. The comprehensive study reveals that the switching behaviour of the device improves considerably due to the incorporation of MGL structure in the central i-region of the device. The device has shown considerably faster reverse recovery time (~ 0.5 ns), low forward RF series resistances (0.29Ω) and low power dissipation (0.45 dB). Central i-region width, doping concentration and mesa diameter of the device are optimized by studying the punch-through effects on the electric field profiles under large signal operation. It is observed that compared to the High-Punch-Through Device (HPTD) and Non-Punch-Through Device (NPTD), Low-Punch-Through Device (LPTD) is showing better high-frequency performances under similar operating conditions. A tradeoff between device width and doping concentration is further established for ultra-fast switching operation in the THz-regime. A comparative analysis of Insertion loss (IL) and Isolation (ISO) in Single-Pole-Single-Throw (SPST), Single-Pole-Double-Throw (SPDT) and Single-Pole-Multi-Throw (SPMT) THz-switches (with series–shunt and Shunt type arrays) is reported in the paper. The study clearly reveals the suitability of LPTD variant for the development of SPST switches in terms of lowest IL (0.015 dB) and SPMT shunt switches in terms of highest ISO (88.0 dB) at around 4.0 THz. Moreover, the authors have made quasi 2D-thermal analysis of the Device-Under-Test (DUT). The results will be extremely useful for developing ultrafast solid-state switches. To the best of authors’ knowledge this is the first ever report on vertically grown MGL-exotic pin (p++–n−–n–n++) device on Si/3C-SiC (100) substrate, as a THz ultrafast switch.

Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the short-channel effects by increasing effective gate lengths but also increase the parasitic capacitances by greater outer fringing electric field. The NSFETs with a crescent inner spacer and slanted source/drain (S/D) increase the physical gate lengths of bottom NS channel, but the anisotropic over-etching of substrate regions induces punchthrough effect at the bottom transistor. Bottom isolation by depositing dielectrics prior to S/D formation is effective to eliminate the punchthrough effect as well as to attain shorter RC delay by better electrostatics and parasitic capacitance reduction. In addition, the isolated S/D NSFETs without punchthrough stopper decrease parasitic and gate capacitances further at the frequency greater than 600 MHz at which the inversion carriers are not formed at the bottom transistor. Thus, although the crescent inner spacer and slanted S/D structure are unintendedly formed under process, these modifications lead to the performance boosting and the process simplicity of the 5-nm node NSFETs.

Reconnoiter the leavening of skin-deep insulated extension on analog performance of RingFET (SDIE-RingFET)

In the present work, a novel device architecture Skin Deep Insulated Extension-RingFET (i.e. SDIE-RingFET) has been reported that incorporates the better known dielectric pocket in RingFET architecture. Various analog performance matrices like ION/IOFF, Vth roll off, Sub-threshold slope (SS), Device efficiency (gm/Ids), conduction band energy (CBE) and electron temperature (TE) have been studied to investigate the impact of Skin Deep Insulated Extension (SDIE) on RingFET architecture. Insulated extension enhances the immunity of the device against Short Channel Effects by reducing IOFF and providing a higher ION/IOFF ratio apart from improved threshold voltage roll-off. In addition, SDIE also prevents dopant diffusion from source/drain to bulk, thereby alleviating the bulk punch-through effect and hence DIBL.

Source-Drain Punch-Through Analysis of High Voltage Off-State AlGaN/GaN HEMT Breakdown

AlGaN/GaN high-electron mobility transistor’s (HEMT’s) off-state breakdown is investigated using conventional three-terminal off-state breakdown I–V measurement. Competition between gate leakage and source-injection buffer leakage (SIBL) is discussed in detail. It is found that the breakdown is dominated by source-injection which is sensitive to gate voltage and gate length at large gate-to-drain spacing (Lgd > 7μm), where a threshold drain voltage of the occurrence of the SIBL current in GaN buffer exists, and after this threshold voltage the SIBL current continually increased till the buffer breakdown. Our analysis showed that due to the punch-through effect in the buffer, a potential barrier between 2DEG and GaN buffer at the source side mainly controlled by the drain voltage determines the buffer leakage current and the occurrence of the following buffer breakdown, which could explain the experimentally observed breakdown phenomenon.